Described herein are techniques that improve the collection and readout of charge carriers in an integrated circuit. Some aspects of the present disclosure relate to integrated circuits having pixels with a plurality of charge storage regions. Some aspects of the present disclosure relate to integrated circuits configured to substantially simultaneously collect and read out charge carriers, at least in part. Some aspects of the present disclosure relate to integrated circuits having a plurality of pixels configured to transfer charge carriers between charge storage regions within each pixel substantially at the same time. Some aspects of the present disclosure relate to integrated circuits having three or more sequentially coupled charge storage regions. Some aspects of the present disclosure relate to integrated circuits capable of increased charge transfer rates. Some aspects of the present disclosure relate to techniques for manufacturing and operating integrated circuits according to the other techniques described herein.

A back-illuminated solid-state imaging device includes a semiconductor substrate, a shift register, and a light-shielding film. The semiconductor substrate includes a light incident surface on the back side and a light receiving portion generating a charge in accordance with light incidence. The shift register is disposed on the side of a light-detective surface opposite to the light incident surface of the semiconductor substrate. The light-shielding film is disposed on the side of the light-detective surface of the semiconductor substrate. The light-shielding film includes an uneven surface opposing the light-detective surface.

A dual-column-parallel image CCD sensor utilizes a dual-column-parallel readout circuit including two pairs of cross-connected transfer gates to alternately transfer pixel data (charges) from a pair of adjacent pixel columns to a shared output circuit at high speed with low noise. Charges transferred along the two adjacent pixel columns at a line clock rate are alternately passed by the transfer gates to a summing gate that is operated at twice the line clock rate to pass the image charges to the shared output circuit. A symmetrical Y-shaped diffusion is utilized in one embodiment to merge the image charges from the two pixel columns. A method of driving the dual-column-parallel CCD sensor with line clock synchronization is also described. A method of inspecting a sample using the dual-column-parallel CCD sensor is also described.

An image reading apparatus includes an image reading chip for reading an image. The image reading chip includes a plurality of pixel units which include a light receiving element which receives light from the image so as to perform photoelectric conversion, an analog circuit, a logic circuit, and a power source pad to which a power source voltage is supplied. The image reading chip has a shape which includes a first side and a second side shorter than the first side. A distance between the analog circuit and a median point of the first side is shorter than a distance between the logic circuit and the median point of the first side, and a distance between the analog circuit and the power source pad is shorter than a distance between the logic circuit and the power source pad.

A solid-state imaging device includes: pixels arranged in a matrix on a semiconductor substrate. Each of the pixels includes: a photoelectric converter that converts received light into a signal charge; at least one read gate that reads the signal charge from the photoelectric converter; charge accumulators that each accumulate the signal charge read by the at least one read gate; and a charge holder that receives, from one of the charge accumulators, transfer of the signal charge accumulated in the charge accumulator, holds the signal charge, and transfers, to one of the charge accumulators, the signal charge held, each of the charge accumulators includes a part of a transfer channel and a part of a transfer electrode overlapping with the part of the transfer channel in a planar view of the semiconductor substrate, and the transfer channel per one pixel comprises transfer channels.

A solid-state imaging device of an embodiment includes plural first transfer gate electrodes, plural second transfer gate electrodes, and plural fixed gate electrodes. The first transfer gate electrodes are such that the respective first transfer gate electrodes are placed in a charge transfer unit to correspond to single light receiving sections, and a control signal ϕ1 is applied. The second transfer gate electrodes are such that the respective second transfer gate electrodes are placed in a charge transfer unit to correspond to the single light receiving sections, and a control signal ϕ2 that differs in phase from the control signal ϕ1 for transferring plural charges is applied. The respective fixed gate electrodes are such that the respective fixed gate electrodes are placed between the first and the second transfer gate electrodes corresponding to the single light receiving sections in the charge transfer unit, and a fixed voltage is applied.

Described herein are techniques that improve the collection and readout of charge carriers in an integrated circuit. Some aspects of the present disclosure relate to integrated circuits having pixels with a plurality of charge storage regions. Some aspects of the present disclosure relate to integrated circuits configured to substantially simultaneously collect and read out charge carriers, at least in part. Some aspects of the present disclosure relate to integrated circuits having a plurality of pixels configured to transfer charge carriers between charge storage regions within each pixel substantially at the same time. Some aspects of the present disclosure relate to integrated circuits having three or more sequentially coupled charge storage regions. Some aspects of the present disclosure relate to integrated circuits capable of increased charge transfer rates. Some aspects of the present disclosure relate to techniques for manufacturing and operating integrated circuits according to the other techniques described herein.

Provided herein include various examples of an apparatus, flow cells that include these examples of the apparatus, and methods of making these examples of the apparatus. The apparatus can include a molding layer over a substrate and covering sides of a light detection device. The molding layer comprises a first region and a second region, which, with the active surface of the light detection device, form a contiguous surface. A waveguide integration layer is between the contiguous surface and a waveguide. The waveguide integration layer comprises optical coupling structures over the first and second regions, to optically couple light waves from a light source to the waveguide. The waveguide utilizes the light waves to excite light sensitive materials in nanowells. A nanostructure layer over the waveguide comprises the nanowells. Each nanowell shares a vertical axis with a location on the active surface of the light detection device.

Described herein are techniques that improve the collection and readout of charge carriers in an integrated circuit. Some aspects of the present disclosure relate to integrated circuits having pixels with a plurality of charge storage regions. Some aspects of the present disclosure relate to integrated circuits configured to substantially simultaneously collect and read out charge carriers, at least in part. Some aspects of the present disclosure relate to integrated circuits having a plurality of pixels configured to transfer charge carriers between charge storage regions within each pixel substantially at the same time. Some aspects of the present disclosure relate to integrated circuits having three or more sequentially coupled charge storage regions. Some aspects of the present disclosure relate to integrated circuits capable of increased charge transfer rates. Some aspects of the present disclosure relate to techniques for manufacturing and operating integrated circuits according to the other techniques described herein.

A time-of-flight (TOF) pixel includes a semiconductor material and a photogate disposed proximate to a frontside of the semiconductor material. The photogate is positioned to transfer charge in the semiconductor material toward the frontside in response to a voltage applied to the photogate. A floating diffusion is disposed in the semiconductor material proximate to the frontside of the semiconductor material, and one or more virtual phase implants is disposed in the semiconductor material proximate to the frontside of the semiconductor material. At least one of the one or more virtual phase implants extend laterally from under the photogate to the floating diffusion to transfer the charge to the floating diffusion.