A nitride semiconductor device includes a substrate, a first electron transport layer above the substrate, a first electron supply layer above the first electron transport layer, a first nitride semiconductor layer above the first electron supply layer, a first opening passing through the first nitride semiconductor layer and the first electron supply layer and reaching the first electron transport layer, a second electron transport layer disposed above the first nitride semiconductor layer and along the inner surface of the first opening, a second electron supply layer disposed above the second electron transport layer and covering the first opening, a gate electrode disposed above the second electron supply layer and covering the first opening, a source electrode connected to the first nitride semiconductor layer and the second electron transport layer, and a drain electrode.

The present disclosure provides a semiconductor structure and a manufacturing method therefor. In the semiconductor structure, a semiconductor substrate, a heterojunction and an in-situ insulation layer are disposed from bottom to top, a trench is provided in the in-situ insulation layer, and a transition layer is located on at least an in-situ insulation layer, the p-type semiconductor layer is located in the trench and on the gate region of the transition layer, and the heavily doped n-type layer is located on at least one of the p-type semiconductor layer in the gate region, the source region of the heterojunction, or the drain region of the heterojunction.

A semiconductor device includes at least one active region, a first dielectric layer, a gate structure, and an air void. The active region includes a III-V compound semiconductor layer. The first dielectric layer is disposed on the active region. The gate structure is disposed on the active region, and at least a part of the gate structure is disposed in the first dielectric layer. The air void is disposed in the first dielectric layer, and at least a part of the air void is disposed at two opposite sides of the gate structure in a horizontal direction.

We disclose a III-nitride semiconductor based heterojunction power device comprising: a first heterojunction transistor formed on a substrate, the first heterojunction transistor comprising: a first III-nitride semiconductor region formed over the substrate, wherein the first III-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas; a first terminal operatively connected to the first III-nitride semiconductor region; a second terminal laterally spaced from the first terminal and operatively connected to the first III-nitride semiconductor region; a first plurality of highly doped semiconductor regions of a first polarity formed over the first III-nitride semiconductor region, the first plurality of highly doped semiconductor regions being formed between the first terminal and the second terminal; a first gate region operatively connected to the first plurality of highly doped semiconductor regions; and a second heterojunction transistor formed on the substrate. The second heterojunction transistor comprises: a second III-nitride semiconductor region formed over the substrate, wherein the second III-nitride semiconductor region comprises a second heterojunction comprising at least one two dimensional carrier gas; a third terminal operatively connected to the second III-nitride semiconductor region; a fourth terminal laterally spaced from the third terminal in the first dimension and operatively connected to the second III-nitride semiconductor region; a second gate region being formed over the second III-nitride semiconductor region, and between the third terminal and the fourth terminal. One of the first and second heterojunction transistors is an enhancement mode field effect transistor and the other of the first and second heterojunction transistors is a depletion mode field effect transistor.

Methods of manufacturing device assemblies, as well as associated semiconductor assemblies, devices, systems are disclosed herein. In one embodiment, a method of forming a semiconductor device assembly includes forming a semiconductor device assembly that includes a handle substrate, a semiconductor structure having a first side and a second side opposite the first side, and an intermediary material between the semiconductor structure and the handle substrate. The method also includes removing material from the semiconductor structure to form an opening extending from the first side of the semiconductor structure to at least the intermediary material at the second side of the semiconductor structure. The method further includes removing at least a portion of the intermediary material through the opening in the semiconductor structure to undercut the second side of the semiconductor structure.

Provided is an electronic device using an interface between BaSnO.sub.3 and LaInO.sub.3, the electronic device including: a substrate formed of a metal oxide of non-SrTiO.sub.3 material a first buffer layer disposed on the substrate and formed of a BaSnO.sub.3 material; a BLSO layer disposed on at least a portion of the first buffer layer and formed of a (Ba.sub.1-x, La.sub.x)SnO.sub.3 material, wherein x has a value equal to or greater than 0 and less than or equal to 1; an LIO layer at least partially disposed on at least a portion of the BLSO layer so as to form an interface between the LIO layer and the BLSO layer, and formed of an LaInO.sub.3 material; and a first electrode layer at least partially in contact with the interface between the BLSO layer and the LIO layer, and formed of at least two or more separated portions.

A trench-type MESFET includes an n-type semiconductor layer including a Ga.sub.2O.sub.3-based single crystal and including plural trenches opening on one surface, first insulators respectively buried in bottom portions of the plural trenches, gate electrodes respectively buried in the plural trenches so as to be placed on the first insulators and so that side surfaces thereof are in contact with the n-type semiconductor layer, a source electrode connected to a mesa-shaped portion between the adjacent trenches of the n-type semiconductor layer, second insulators respectively buried in the plural trenches so as to be placed on the gate electrodes to insulate the gate electrodes and the source electrode, and a drain electrode directly or indirectly connected to the n-type semiconductor layer on a side opposite to the source electrode.

A method for manufacturing nitride semiconductor device includes a second step of forming, on a gate layer material film, a gate electrode film that is a material film of a gate electrode, a third step of selectively etching the gate electrode film to form the gate electrode 22 of a ridge shape, and a fourth step of selectively etching the gate layer material film to form a semiconductor gate layer 21 of a ridge shape with the gate electrode 22 disposed at a width intermediate portion of a front surface thereof. The third step includes a first etching step for forming a first portion 22A from an upper end to a thickness direction intermediate portion of the gate electrode 22 and a second etching step being a step differing in etching condition from the first etching step and being for forming a remaining second portion 22B of the gate electrode.

A nitride semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer formed on the first nitride semiconductor layer, a third nitride semiconductor layer that is disposed on the second nitride semiconductor layer, has a ridge portion at least at a portion thereof, and contains an acceptor type impurity, a gate electrode that is disposed on the ridge portion, and a source electrode and a drain electrode that, on the second nitride semiconductor layer, are disposed across the ridge portion from each other, and has an active region and a nonactive region. The nonactive region has a first region and a film thickness of the second nitride semiconductor layer in the first region differs from a film thickness of the second nitride semiconductor layer in a region of the active region in which the ridge portion, the source electrode, and the drain electrode are not formed.

The present disclosure relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The structure includes: a gate structure comprising a horizontal portion and a substantially vertical stem portion; and an air gap surrounding the substantially vertical stem portion and having a curved surface under the horizontal portion.