A transistor includes a wide bandgap semiconductor layer, a gate electrode, a gate pad, and a gate runner. The gate electrode extends to a region where the gate pad is located and a region where the gate runner is located. The gate pad is connected to the gate electrode. The gate runner is connected to the gate electrode. The gate electrode includes a first region connected to the gate pad, a second region connected to the gate runner, and a third region and a fourth region arranged between the first and second regions in different positions in a first direction. In a cross section perpendicular to the first direction, the gate electrode in the fourth region has a cross-sectional area smaller than that of the gate electrode in the third region.

Field-effect transistors, and integrated circuit devices containing such field-effect transistors, might include a semiconductor material having a first conductivity type, a first source/drain region having a second conductivity type, a second source/drain region having the second conductivity type, a first contact connected to the first source/drain region, a conductor overlying an active area of the semiconductor material and having an annular portion surrounding the first contact and a spur portion extending from an outer perimeter of the annular portion of the conductor, a second contact connected to the second source/drain region outside the annular portion of the conductor, a dielectric between the conductor and the active area, and a third contact overlying the active area and connected to the spur portion of the conductor.

A power semiconductor device includes an active cell region with a drift region of a first conductivity type, a plurality of IGBT cells arranged within the active cell region, each of the IGBT cells includes at least one trench that extends into the drift, an edge termination region surrounding the active cell region, a transition region arranged between the active cell region and the edge termination region, at least some of the IGBT cells are arranged within or extend into the transition region, a barrier region of a second conductivity type, the barrier region is arranged within the active cell region and in contact with at least some of the trenches of the IGBT cells and does not extend into the transition region, and a first load terminal and a second load terminal, the power semiconductor device is configured to conduct a load current along a vertical direction between.

A semiconductor-on-insulator (SOI) transistor includes a semiconductor layer situated over a buried oxide layer, the buried oxide layer being situated over a substrate. The SOI transistor is situated in the semiconductor layer and includes a transistor body, gate fingers, source regions, and drain regions. The transistor body has a first conductivity type. The source regions and the drain regions have a second conductivity type opposite to the first conductivity type. A heavily-doped body-implant region has the first conductivity type and overlaps at least one source region. A common silicided region electrically ties the heavily-doped body-implant region to the at least one source region. The common silicided region can include a source silicided region, and a body tie silicided region situated over the heavily-doped body-implant region. The source silicided region can be separated from a drain silicided region by the gate fingers.

An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

A trench-gate MOSFET with electric field shielding region, has a substrate; a source electrode; a drain electrode; a semiconductor region with a first doping type formed on the substrate; a trench-gate, a plurality of electric field shielding regions with a second doping type formed under a surface of the semiconductor region, wherein the electric field shielding region intersects the trench-gate at an angle; a source electrode region formed on both sides of the trench-gate is divided into a plurality of source electrode sub-regions by the plurality of electric field shielding regions.

Provided is a semiconductor device including: a buffer region having a doping concentration higher than a bulk donor concentration; a first low-concentration hydrogen peak in the buffer region; a second low-concentration hydrogen peak in the buffer region closer to a lower surface than the first low-concentration hydrogen peak; a high-concentration hydrogen peak in the buffer region closer to the lower surface than the second low-concentration hydrogen peak, the high-concentration hydrogen peak having a hydrogen chemical concentration higher than that of the second low-concentration hydrogen peak; and a flat region including a region between the two low-concentration hydrogen peaks and a region including the second low-concentration hydrogen peak, and having a doping concentration higher than a bulk donor concentration, an average value of the doping concentration being equal to or smaller than a local minimum value of a doping concentration between the second low-concentration hydrogen peak and the high-concentration hydrogen peak.

Provided is a semiconductor device including: a semiconductor substrate having a drift region of a first conductivity type; and a buffer region of the first conductivity type provided between the drift region and a lower surface of the semiconductor substrate and having a higher doping concentration than the drift region. The buffer region has two or more helium chemical concentration peaks arranged at different positions in a depth direction of the semiconductor substrate.

In a method of manufacturing a semiconductor device, first and second fin structures are formed over a substrate, an isolation insulating layer is formed over the substrate, a gate structure is formed over channel regions of the first and second fin structures, source/drain regions of the first and second fin structure are recessed, and an epitaxial source/drain structure is formed over the recessed first and second fin structures. The epitaxial source/drain structure is a merged structure having a merger point, and a height of a bottom of the merger point from an upper surface of the isolation insulating layer is 50% or more of a height of the channel regions of the first and second fin structures from the upper surface of the isolation insulating layer.

A method of processing a power semiconductor device includes: providing a semiconductor body with a drift region of a first conductivity type; forming a plurality of trenches extending into the semiconductor body along a vertical direction and arranged adjacent to each other along a first lateral direction; providing a mask arrangement at the semiconductor body, the mask arrangement having a lateral structure according to which some of the trenches are exposed and at least one of the trenches is covered by the mask arrangement along the first lateral direction; forming, below bottoms of the exposed trenches, a plurality of doping regions of a second conductivity type complementary to the first conductivity type; removing the mask arrangement; and extending the plurality of doping regions in parallel to the first lateral direction such that the plurality of doping regions overlap and form a barrier region of the second conductivity type adjacent to the bottoms of the exposed trenches.