H01L29/42396

MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND WRAPPED DATA LINE STRUCTURE

Some embodiments include apparatuses and methods forming the apparatuses. One of the apparatuses includes a first transistor including a first channel region, and a charge storage structure separated from the first channel region; a second transistor including a second channel region formed over the charge storage structure; and a data line formed over and contacting the first channel region and the second channel region, the data line including a portion adjacent the first channel region and separated from the first channel region by a dielectric material.

Memory device having 2-transistor vertical memory cell and wrapped data line structure

Some embodiments include apparatuses and methods forming the apparatuses. One of the apparatuses includes a first transistor including a first channel region, and a charge storage structure separated from the first channel region; a second transistor including a second channel region formed over the charge storage structure; and a data line formed over and contacting the first channel region and the second channel region, the data line including a portion adjacent the first channel region and separated from the first channel region by a dielectric material.

3D INTEGRATED CHARGE-COUPLED DEVICE MEMORY AND METHOD OF FABRICATING THE SAME

A charge-coupled device (CCD) memory is provided. In one aspect, the CCD memory is 3D integrated. The CCD memory can include a gate stack with a plurality of gate layers and spacer layers alternatingly arranged one on the other, and a plurality of semiconductor-based channels extending in the stack. The channels may be formed from a semiconductor oxide material. The CCD memory can include dielectric layers, wherein each dielectric layer is arranged between one of the channels and at least one of the gate layers. Each channel of the CCD memory can form, in combination with the gate layers and at least one of the dielectric layers, a string of charge storage capacitors, and each string of charge storage capacitors can be operable as a CCD register. The CCD memory can also include a readout layer, which can include a plurality of readout stages configured to individually readout stored charge from each of the CCD registers.

NON-VOLATILE MEMORY SYSTEMS BASED ON SINGLE NANOPARTICLES FOR COMPACT AND HIGH DATA STORAGE ELECTRONIC DEVICES
20220005932 · 2022-01-06 ·

There is provided a structure of a nano memory system. The disclosed unit nano memory cell comprises a single isolated nanoparticle placed on the surface of a semiconductor substrate (301) and an adjacent nano-Schottky contact (303). The nanoparticle works as a storage site where the nano-Schottky contact (303) works as a source or a drain of electrons, in or out of the semiconductor substrate (301), at a relatively small voltage. The electric current through the nano-Schottky contact (303) can be turned on (reading 1) or off (reading 0) by charging or discharging the nanoparticle. Since the electric contact is made by a nano-Scottky contact (303) on the surface and the back contact of the substrate (301), and the charge is stored in a very small nanoparticle, this allows to attain the ultimate device down-scaling. This would also significantly increase the number of nano memory cells on a chip. Moreover, the charging and discharging (writing/erasing), as well as the reading voltages are lower than those needed for CMOS based flash memory cells, due to the small nano-Schottky contact (301) and the small size of the nanoparticle for charge storage.

Memory device having 2-transistor vertical memory cell and wrapped data line structure

Some embodiments include apparatuses and methods forming the apparatuses. One of the apparatuses includes a first transistor including a first channel region, and a charge storage structure separated from the first channel region; a second transistor including a second channel region formed over the charge storage structure; and a data line formed over and contacting the first channel region and the second channel region, the data line including a portion adjacent the first channel region and separated from the first channel region by a dielectric material.

Image pickup apparatus having wiring board with alternately arranged flying leads
10334143 · 2019-06-25 · ·

An image pickup apparatus includes: an image pickup device including a light receiving surface, an opposite surface, and an inclined surface inclined at a first angle, and provided with light receiving surface electrodes on the light receiving surface; a cover glass; and a wiring board including a first main surface and a second main surface, and including wires each connected with each of the light receiving surface electrodes, back surfaces of the light receiving surface electrodes are exposed to a side of the opposite surface, distal end portions of the wires are flying leads bent at a second angle in a relation of a supplementary angle to the first angle and connected with the light receiving surface electrodes, and the second main surface at a distal end portion of the wiring board is directly fixed to the opposite surface arranged in parallel with the second main surface.

Semiconductor device, memory circuit, method of manufacturing semiconductor device
10269867 · 2019-04-23 · ·

A semiconductor device of the technology includes a first diffusion section (22), a second diffusion section (21), a channel section (23), a gate section (24), and a stress application section (31, 32, or 33). In a semiconductor layer (10) having a groove (10A), the first diffusion section (22) is formed at or in the vicinity of a bottom of the groove (10A), the second diffusion section (21) is formed at an upper end of the groove (10A), and the channel section (23) is formed between the first diffusion section (22) and the second diffusion section (21). The gate section (24) is buried in the groove (10A) at a position opposing the channel section (23). The stress application section (31, 32, or 33) applies one of compressive stress and tensile stress to the channel section (23) in a normal direction to the semiconductor layer (10).

MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND WRAPPED DATA LINE STRUCTURE

Some embodiments include apparatuses and methods forming the apparatuses. One of the apparatuses includes a first transistor including a first channel region, and a charge storage structure separated from the first channel region; a second transistor including a second channel region formed over the charge storage structure; and a data line formed over and contacting the first channel region and the second channel region, the data line including a portion adjacent the first channel region and separated from the first channel region by a dielectric material.

IMAGE PICKUP APPARATUS
20180041666 · 2018-02-08 · ·

An image pickup apparatus includes: an image pickup device including a light receiving surface, an opposite surface, and an inclined surface inclined at a first angle, and provided with light receiving surface electrodes on the light receiving surface; a cover glass; and a wiring board including a first main surface and a second main surface, and including wires each connected with each of the light receiving surface electrodes, back surfaces of the light receiving surface electrodes are exposed to a side of the opposite surface, distal end portions of the wires are flying leads bent at a second angle in a relation of a supplementary angle to the first angle and connected with the light receiving surface electrodes, and the second main surface at a distal end portion of the wiring board is directly fixed to the opposite surface arranged in parallel with the second main surface.