An object is to provide a display device with excellent display characteristics, where a pixel circuit and a driver circuit provided over one substrate are formed using transistors which have different structures corresponding to characteristics of the respective circuits. The driver circuit portion includes a driver circuit transistor in which a gate electrode layer, a source electrode layer, and a drain electrode layer are formed using a metal film, and a channel layer is formed using an oxide semiconductor. The pixel portion includes a pixel transistor in which a gate electrode layer, a source electrode layer, and a drain electrode layer are formed using an oxide conductor, and a semiconductor layer is formed using an oxide semiconductor. The pixel transistor is formed using a light-transmitting material, and thus, a display device with higher aperture ratio can be manufactured.

Disclosed are film packages and methods of fabricating package modules. The film package includes a film substrate that includes a chip region and a peripheral region facing each other in a first direction, a plurality of output pads that are arranged in the first direction on the chip region and on the peripheral region, and a semiconductor chip on the chip region and electrically connected to the output pads. The output pads on the chip region are arranged at regular first intervals along the first direction. The output pads include a plurality of first output pads that are arranged at a first pitch along the first direction on the chip region and a plurality of second output pads on the peripheral region. The second output pads are arranged at a second pitch greater than the first pitch of the first output pads.

Structures and fabrication methods for a vertical-transport field-effect transistor. A plurality of pillars comprised of a semiconductor material are formed. First and second gate structures are located along a length of the pillars. The second gate structure is vertically spaced along the length of the pillars relative to the first gate structure. The first and second gate structures are each associated with a channel defined in the pillars.

An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel.

A pair of ground planes arranged in parallel, a dielectric medium disposed in between the pair of ground planes, and a set of at least four signal conductors disposed in the dielectric medium, the set of at least four signal conductors having (i) a first pair of signal conductors arranged proximate to a first ground plane of the pair of ground planes and (ii) a second pair of signal conductors arranged proximate to a second ground plane of the pair of ground planes, each signal conductor of the set of at least four signal conductors configured to carry a respective signal corresponding to a symbol of a codeword of a vector signaling code.

A charge-coupled device (CCD) memory is provided. In one aspect, the CCD memory is 3D integrated. The CCD memory can include a gate stack with a plurality of gate layers and spacer layers alternatingly arranged one on the other, and a plurality of semiconductor-based channels extending in the stack. The channels may be formed from a semiconductor oxide material. The CCD memory can include dielectric layers, wherein each dielectric layer is arranged between one of the channels and at least one of the gate layers. Each channel of the CCD memory can form, in combination with the gate layers and at least one of the dielectric layers, a string of charge storage capacitors, and each string of charge storage capacitors can be operable as a CCD register. The CCD memory can also include a readout layer, which can include a plurality of readout stages configured to individually readout stored charge from each of the CCD registers.

A pair of ground planes arranged in parallel, a dielectric medium disposed in between the pair of ground planes, and a set of at least four signal conductors disposed in the dielectric medium, the set of at least four signal conductors having (i) a first pair of signal conductors arranged proximate to a first ground plane of the pair of ground planes and (ii) a second pair of signal conductors arranged proximate to a second ground plane of the pair of ground planes, each signal conductor of the set of at least four signal conductors configured to carry a respective signal corresponding to a symbol of a codeword of a vector signaling code.

A semiconductor device includes a substrate, semiconductor 2-D material layer, a conductive 2-D material layer, a gate dielectric layer, and a gate electrode. The semiconductor 2-D material layer is over the substrate. The conductive 2-D material layer extends along a source/drain region of the semiconductor 2-D material layer, in which the conductive 2-D material layer comprises a group-IV element. The gate dielectric layer extends along a channel region of the semiconductor 2-D material layer. The gate electrode is over the gate dielectric layer.

A semiconductor device includes a substrate, semiconductor 2-D material layer, a conductive 2-D material layer, a gate dielectric layer, and a gate electrode. The semiconductor 2-D material layer is over the substrate. The conductive 2-D material layer extends along a source/drain region of the semiconductor 2-D material layer, in which the conductive 2-D material layer comprises a group-IV element. The gate dielectric layer extends along a channel region of the semiconductor 2-D material layer. The gate electrode is over the gate dielectric layer.

A method of forming an active device having self-aligned source/drain contacts and gate contacts, including, forming an active area on a substrate, where the active area includes a device channel; forming two or more gate structures on the device channel; forming a plurality of source/drains on the active area adjacent to the two or more gate structures and device channel; forming a protective layer on the surfaces of the two or more gate structures, plurality of source/drains, and active layer; forming an interlayer dielectric layer on the protective layer; removing a portion of the interlayer dielectric and protective layer to form openings, where each opening exposes a portion of one of the plurality of source/drains; forming a source/drain contact liner in at least one of the plurality of openings; and forming a source/drain contact fill on the source/drain contact liner.