A first phase adjuster adjusts the phase of any one of first and second AC voltages generated in a negative resistance circuit so that a shift amount Φ in a first variable phase shifter falls within a range of 0 degrees≤Φ<180 degrees, and outputs the phase-adjusted AC voltage to the first variable phase shifter, and a second phase adjuster adjusts the phase of the other one of the first and second AC voltages generated in the negative resistance circuit so that a shift amount Φ in a second variable phase shifter falls within a range of 0 degrees≤Φ<180 degrees, and outputs the phase-adjusted AC voltage to the second variable phase shifter.

Systems and methods for integrating injection-locked oscillators into transceiver arrays are disclosed. In one aspect, there is provided an injection-locked oscillator (ILO) distribution system including a master clock generator configured to generate a master clock signal. The ILO distribution system also includes an ILO distribution circuit including an ILO and configured to receive the master clock signal. The ILO is configured to generate a reference clock signal based on the master clock signal. The ILO distribution circuit is further configured to generate an output signal indicative of an operating frequency of the ILO. The ILO distribution system further includes an injection-locked detector (ILD) configured to receive the master clock signal and the output signal. The ILD is further configured to determine whether the ILO is in a locked state or in an unlocked state based on the master clock signal and the output signal.

Systems and methods for integrating injection-locked oscillators into transceiver arrays are disclosed. In one aspect, there is provided an injection-locked oscillator (ILO) distribution system including a master clock generator configured to generate a master clock signal. The ILO distribution system also includes an ILO distribution circuit including an ILO and configured to receive the master clock signal. The ILO is configured to generate a reference clock signal based on the master clock signal. The ILO distribution circuit is further configured to generate an output signal indicative of an operating frequency of the ILO. The ILO distribution system further includes an injection-locked detector (ILD) configured to receive the master clock signal and the output signal. The ILD is further configured to determine whether the ILO is in a locked state or in an unlocked state based on the master clock signal and the output signal.

Circuits and processes for locking a voltage-controlled oscillator (VCO) at a high frequency signal are described. A circuit may include an adjustable current converter (ACC), coupled at an input terminal to a power source, operable to output a control signal (VC) at an output terminal. A first switch may be coupled to the ACC and to the VCO. The VCO, when in an “ON” state, receives the control signal and outputs a high frequency signal (VHF). A digital filter may be coupled to the VCO and operable to receive the VHF. Based on the VHF, the digital filter generates a data signal having a data value. The circuit may also include a digital-to-analog converter (DAC) operable to receive the data signal and, based on the data value, output an adjustment signal to the ACC. The ACC may adjust the control signal based on the adjustment signal received from the DAC.

A phase-locked loop comprises a voltage controlled oscillator. The voltage controlled oscillator comprises an inductor and a capacitor, connected in parallel, and also connected in parallel therewith, a negative resistance structure. A first terminal of the negative resistance structure is connected to respective first terminals of the inductor and the capacitor. A second terminal of the negative resistance structure is connected to respective second terminals of the inductor and the capacitor. The negative resistance structure exhibits a tunable capacitance, such that a frequency of an output of the voltage controlled oscillator can be tuned by a control input signal, and the control input signal is generated in the phase-locked loop. The negative resistance structure comprises first and second transistors. There is a first conduction path between the first terminal of the first transistor and the control terminal of the second transistor, and a second conduction path between the control terminal of the first transistor and the first terminal of the second transistor. The control terminal of at least one of the first and second transistors is biased by the control input signal, such that a parasitic capacitance of said at least one of the first and second transistors can be tuned by the control input signal, in order to tune the frequency of the output of the voltage controlled oscillator, and hence the frequency of oscillation of the phase-locked loop.

An oscillator circuit (15) is disclosed. It comprises N amplifier circuits (A.sub.1-A.sub.4), connected in a ring and has a first and a second supply terminal (s.sub.1, s.sub.2). Each amplifier circuit (A.sub.1-A.sub.4) comprises an input transistor (M.sub.1) having its gate connected to the input (in) of the amplifier circuit, its drain connected to an internal node (x) of the amplifier circuit, and its source connected to the first supply terminal (si). Furthermore, each amplifier circuit (A.sub.1-A.sub.4) comprises a first resonance circuit (R.sub.1) comprising a first inductor (L.sub.s) and a first capacitor (C.sub.s), wherein the first inductor (L.sub.s) is connected between the internal node (x) and the output (out) of the amplifier circuit, and the first capacitor (C.sub.s) is connected between the output (out) of the amplifier circuit and one of the first and the second supply terminals (s.sub.1, s.sub.2). Moreover, each amplifier circuit (A.sub.1-A.sub.4) comprises a second resonance circuit (R.sub.2) comprising a second inductor (L.sub.p) and a second capacitor (C.sub.p), wherein the second inductor (L.sub.p) and the second capacitor (C.sub.p) are connected in parallel between the internal node (x) and the second supply terminal (s.sub.2).

An oscillator configured to generate an oscillation signal is provided. The oscillator includes a transistor pair and a cross-coupled transistor pair. The transistor pair is coupled to a first current source and has a first transconductance. The first transconductance is changed in response to a current value of the first current source. The cross-coupled transistor pair is coupled to a second current source and has a second transconductance. The second transconductance is changed in response to a current value of second current source. The transistor pair and the cross-coupled transistor pair are mutually coupled by a plurality of inductors. A frequency of the oscillation signal is determined according to the first transconductance and the second transconductance. Furthermore, a clock generator and a method for generating a clock signal thereof are also provided.

Systems and methods for integrating injection-locked oscillators into transceiver arrays are disclosed. In one aspect, there is provided an injection-locked oscillator (ILO) distribution system including a master clock generator configured to generate a master clock signal. The ILO distribution system also includes an ILO distribution circuit including an ILO and configured to receive the master clock signal. The ILO is configured to generate a reference clock signal based on the master clock signal. The ILO distribution circuit is further configured to generate an output signal indicative of an operating frequency of the ILO. The ILO distribution system further includes an injection-locked detector (ILD) configured to receive the master clock signal and the output signal. The ILD is further configured to determine whether the ILO is in a locked state or in an unlocked state based on the master clock signal and the output signal.

Circuits and processes for locking a voltage-controlled oscillator (VCO) at a high frequency signal are described. A circuit may include a voltage-controlled oscillator configured to generate a high frequency signal based on a control signal, a dummy load parallel to the voltage-controlled oscillator and configured to receive the control signal via a switch, and a digital-to-analog converter coupled to the voltage-controlled oscillator where the control signal is generated based on an output of the digital-to-analog converter.

An oscillator circuit (15) is disclosed. It comprises N amplifier circuits (A.sub.1-A.sub.4), connected in a ring and has a first and a second supply terminal (s.sub.1, s.sub.2). Each amplifier circuit (A.sub.1-A.sub.4) comprises an input transistor (M.sub.1) having its gate connected to the input (in) of the amplifier circuit, its drain connected to an internal node (x) of the amplifier circuit, and its source connected to the first supply terminal (si). Furthermore, each amplifier circuit (A.sub.1-A.sub.4) comprises a first resonance circuit (R.sub.1) comprising a first inductor (L.sub.s) and a first capacitor (C.sub.s), wherein the first inductor (L.sub.s) is connected between the internal node (x) and the output (out) of the amplifier circuit, and the first capacitor (C.sub.s) is connected between the output (out) of the amplifier circuit and one of the first and the second supply terminals (s.sub.1, s.sub.2). Moreover, each amplifier circuit (A.sub.1-A.sub.4) comprises a second resonance circuit (R.sub.2) comprising a second inductor (L.sub.p) and a second capacitor (C.sub.p), wherein the second inductor (L.sub.p) and the second capacitor (C.sub.p) are connected in parallel between the internal node (x) and the second supply terminal (s.sub.2).