H03F3/45112

BLEEDER CIRCUITRY FOR AN ELECTRONIC DEVICE
20220352855 · 2022-11-03 ·

Devices and methods include voltage buses. The devices also include one or more power amplifiers coupled to the voltage bus. Each of the one or more power amplifiers include one or more transistors. The devices also include a model that is configured to emulate leakage from at least one of the one or more transistors. A current mirror with a first transistor coupled to the model and a second transistor coupled to the voltage bus. The current mirror is configure to draw charge from the voltage bus based at least in part on the emulated leakage from the model.

Bleeder circuitry for an electronic device
11545940 · 2023-01-03 · ·

Devices and methods include voltage buses. The devices also include one or more power amplifiers coupled to the voltage bus. Each of the one or more power amplifiers include one or more transistors. The devices also include a model that is configured to emulate leakage from at least one of the one or more transistors. A current mirror with a first transistor coupled to the model and a second transistor coupled to the voltage bus. The current mirror is configure to draw charge from the voltage bus based at least in part on the emulated leakage from the model.

CMOS input stage circuits and related methods

Embodiments of improved CMOS input stage circuits and related methods are provided herein to maintain a near constant transconductance across an entire common-mode input voltage range of the input stage. One embodiment includes a pair of NMOS input transistors and a pair of PMOS input transistors, each coupled to receive a differential input voltages at their gate terminals; a current source coupled to source terminals of the pair of PMOS input transistors and configured to generate a current; a current steering circuit configured to steer the current to the pair of NMOS input transistors and/or to the pair of PMOS input transistors, depending on whether a common mode input voltage (CMV) is greater than, less than, or substantially equal to a cross-over voltage; and a current stealing circuit configured to reduce the current when the CMV is substantially equal to the cross-over voltage.

CMOS Input Stage Circuits And Related Methods
20200389140 · 2020-12-10 ·

Embodiments of improved CMOS input stage circuits and related methods are provided herein to maintain a near constant transconductance across an entire common-mode input voltage range of the input stage. One embodiment includes a pair of NMOS input transistors and a pair of PMOS input transistors, each coupled to receive a differential input voltages at their gate terminals; a current source coupled to source terminals of the pair of PMOS input transistors and configured to generate a current; a current steering circuit configured to steer the current to the pair of NMOS input transistors and/or to the pair of PMOS input transistors, depending on whether a common mode input voltage (CMV) is greater than, less than, or substantially equal to a cross-over voltage; and a current stealing circuit configured to reduce the current when the CMV is substantially equal to the cross-over voltage.

Class-F power amplifier matching network

A class-F power amplifier (PA) with a matching network is disclosed herein. The class-F PA comprises a first switch and a second switch operating in differential mode, with a second harmonic trap circuitry selectively terminating the drain terminals to ground at a second harmonic frequency. The second harmonic trap circuitry comprises a plurality of lumped inductive and capacitive components. The PA further comprises a common mode trap and a matching network to reduce the imbalance of the drain terminal impedance between first harmonics and third harmonics.

CLASS-F POWER AMPLIFIER MATCHING NETWORK
20180205349 · 2018-07-19 ·

A class-F power amplifier (PA) with a matching network is disclosed herein. The class-F PA comprises a first switch and a second switch operating in differential mode, with a second harmonic trap circuitry selectively terminating the drain terminals to ground at a second harmonic frequency. The second harmonic trap circuitry comprises a plurality of lumped inductive and capacitive components. The PA further comprises a common mode trap and a matching network to reduce the imbalance of the drain terminal impedance between first harmonics and third harmonics.

INPUT STAGE CIRCUIT FOR AN OPERATIONAL AMPLIFIER WITH ENHANCED INPUT OFFSET VOLTAGE TRIMMING CAPABILITIES
20250088158 · 2025-03-13 ·

An input stage circuit for an operational amplifier includes first and second differential pairs connected in parallel between positive and negative input terminals. Each differential pair comprises a pair of transistors that are intentionally and systematically mismatched. The mismatching of each transistor pair creates a pre-trim input offset voltage for the circuit. However, a unique current is utilized to bias each of the first and second differential pairs. By adjusting the differential between the bias currents, a composite input offset voltage is created that combines with the pre-trim input offset voltage to yield a total input offset voltage for the circuit that approaches zero. Additionally, adjusting the differential between the bias currents simultaneously trims the temperature coefficient of the total input offset voltage to zero while using limited power and producing minimal noise.

Buffer circuit having amplifier offset compensation and source driving circuit including the same

Provided are an output buffer circuit having an amplifier offset compensation function and a source driving circuit including the output buffer circuit. The output buffer circuit may include a plurality of channel amplifiers, each of which is configured to adjust an amount of current flowing through transistors connected to at least one of a non-inverted input terminal and an inverted input terminal of a differential input unit to compensate an amplifier offset, and adjust buffer input voltage signals to generate output voltage signals.

HIGH-PERFORMANCE AUDIO AMPLIFIER

The invention relates to a high-performance audio amplifier intended to control at least one loudspeaker, the amplifier comprising a pre-amplification stage that receives an input signal, a power amplification stage connected to the pre-amplification stage and a feedback that delivers to the pre-amplification stage an image of the output signal, the power amplification stage comprising two power supply circuits comprising a MOSFET transistor. The invention is characterized in that it comprises: a sub-circuit for assisting with charging, a sub-circuit for assisting with discharging said MOSFET transistor, and a voltage-shifting sub-circuit.

High-performance audio amplifier

The invention relates to a high-performance audio amplifier intended to control at least one loudspeaker, the amplifier comprising a pre-amplification stage that receives an input signal, a power amplification stage connected to the pre-amplification stage and a feedback that delivers to the pre-amplification stage an image of the output signal, the power amplification stage comprising two power supply circuits comprising a MOSFET transistor. The invention is characterized in that it comprises: a sub-circuit for assisting with charging, a sub-circuit for assisting with discharging said MOSFET transistor, and a voltage-shifting sub-circuit.