A data transmitter includes: a plurality of parallel driver slices, a first slice of the plurality of parallel driver slices having a first signal generator circuit with a first transistor coupled to a data signal and in series with a second transistor coupled to a first bias signal; and a first bias circuit including a third transistor and a fourth transistor in series with a first current source, the first bias circuit further including a first operational amplifier (op amp) having a first input coupled to a first reference voltage and a second input coupled between the fourth transistor and the first current source, an output of the first op amp configured to provide the first bias signal to the second transistor and to the third transistor.

A multi-stage amplifier including a pre-driver stage, and method of operating the same. In one example, the amplifier includes an output stage with a first output transistor coupled to an oppositely doped second output transistor and to an output terminal. The pre-driver stage includes with a first driver transistor coupled to the first output transistor, and a second driver transistor coupled to the second output transistor. The pre-driver stage also includes a first current mirror and a second current mirror coupled to the first driver transistor and the second driver transistor. The pre-driver stage also includes a first translinear loop having a first translinear loop transistor and a second translinear loop having a second translinear loop transistor coupled to the first output transistor and the second output transistor.

A data transmitter includes: a plurality of parallel driver slices, a first slice of the plurality of parallel driver slices having a first signal generator circuit with a first transistor coupled to a data signal and in series with a second transistor coupled to a first bias signal; and a first bias circuit including a third transistor and a fourth transistor in series with a first current source, the first bias circuit further including a first operational amplifier (op amp) having a first input coupled to a first reference voltage and a second input coupled between the fourth transistor and the first current source, an output of the first op amp configured to provide the first bias signal to the second transistor and to the third transistor.

A multi-stage amplifier including a pre-driver stage, and method of operating the same. In one example, the amplifier includes an output stage with a first output transistor coupled to an oppositely doped second output transistor and to an output terminal. The pre-driver stage includes with a first driver transistor coupled to the first output transistor, and a second driver transistor coupled to the second output transistor. The pre-driver stage also includes a first current mirror and a second current mirror coupled to the first driver transistor and the second driver transistor. The pre-driver stage also includes a first translinear loop having a first translinear loop transistor and a second translinear loop having a second translinear loop transistor coupled to the first output transistor and the second output transistor.

A voltage controlled amplifier with an amplitude limiting circuit, such as a clip limiter, that is separate from the signal path on which the input signal is received by a power amplifier can reduce both noise and power expenditure of the voltage controlled amplifier. The amplitude limiting circuit can include a transistor network that is controlled by a pair of utility operational amplifiers. These utility amplifiers may use less current than the audio amplifier of the voltage controlled amplifier. Further, the transistor network can be deactivated when a signal supplied to the voltage controlled amplifier is below a clipping or other voltage limiting threshold.

A voltage controlled amplifier with an amplitude limiting circuit, such as a clip limiter, that is separate from the signal path on which the input signal is received by a power amplifier can reduce both noise and power expenditure of the voltage controlled amplifier. The amplitude limiting circuit can include a transistor network that is controlled by a pair of utility operational amplifiers. These utility amplifiers may use less current than the audio amplifier of the voltage controlled amplifier. Further, the transistor network can be deactivated when a signal supplied to the voltage controlled amplifier is below a clipping or other voltage limiting threshold.

A driver circuit includes a driver array configured to generate, at a first output, a multi-bit output signal including a first bit associated with a predetermined first-bit amplitude and a second bit associated with a predetermined second-bit amplitude. The driver array includes first-bit driver slices coupled in parallel between a first input of first data associated with the first bit and the first output, and second-bit driver slices coupled in parallel between a second input of second data associated with the second bit and the first output. A first ratio between a first number of enabled first-bit driver slices and a second number of enabled second-bit driver slices is different from a second ratio between the predetermined first-bit amplitude and the predetermined second-bit amplitude.

A voltage-to-current converter includes a first differential pair of transistors, a second differential pair of transistors, and a first resistor. The first differential pair of transistors includes a first transistor and a second transistor. An emitter of the first transistor is directly connected to an emitter of the second transistor. The second differential pair of transistors includes a third transistor and a fourth transistor. An emitter of the third transistor is directly connected to an emitter of the fourth transistor. The first resistor is connected to the emitter of the first transistor, the emitter of the second transistor, the emitter of the third transistor, and the emitter of the fourth transistor.

A device is disclosed that includes a first gain stage and a first amplifier. The first gain stage is configured to generate a first signal according to a first input signal, and to multiply the first signal and the first input signal, to generate a second signal at a first output terminal, in which the first signal is associated with the even order signal components of the first input signal. The first amplifier is configured to amplify the first input signal to generate a third signal at the first output terminal, in order to output a first output signal with the first gain stage, in which the first output signal is the sum of the second signal and the third signal.

A device is disclosed that includes a first gain stage and a first amplifier. The first gain stage is configured to generate a first signal according to a first input signal, and to multiply the first signal and the first input signal, to generate a second signal at a first output terminal, in which the first signal is associated with the even order signal components of the first input signal. The first amplifier is configured to amplify the first input signal to generate a third signal at the first output terminal, in order to output a first output signal with the first gain stage, in which the first output signal is the sum of the second signal and the third signal.