Speed enhancement of data reading is achieved while suppressing an influence of an offset voltage of a differential amplifier. The differential amplifier includes: a current source that is connected to a first power supply in which a suppliable current is a first current; an active element pair that is connected to the current source, and amplifies a signal input to an input terminal pair to output an output signal pair; a load element pair that is connected to a second power supply different in power supply voltage from the first power supply, the load element pair serving for outputting the output signal pair to an output terminal pair; and a capacitance element pair that is inserted between an external input terminal pair and the input terminal pair; a switching element pair that charges the capacitance element pair to generate a voltage, which is obtained by converting an offset voltage of the input terminal pair into an input voltage, in the capacitance element pair by short-circuiting corresponding terminals between the output terminal pair and the input terminal pair; and a current control circuit that controls a current suppliable by the current source to a second current larger than the first current at a time of performing the charge.

An amplifier for converting a differential input signal to a single ended output signal. In particular, the amplifier including a converting circuit for converting a differential input signal into a single ended output signal, the converting circuit including an input section for receiving the differential input signal and an output section including an output port for providing the single ended output signal, where the output section includes a capacitive element configured to reduce an intrinsic time constant of the converting circuit.

A leakage compensation circuit includes a buffer amplifier, a link coupling element, and a leakage compensation element. The buffer amplifier has an input coupled to a sense node, and an output. The link coupling element has an input coupled to the output of the buffer amplifier, and an output, wherein the link coupling element is unidirectional in a direction from the input to the output thereof. The leakage compensation element has a first current terminal coupled to the sense node, a control terminal coupled to the output of the link coupling element, and a second current terminal coupled to a reference voltage terminal.

A leakage compensation circuit includes a buffer amplifier, a link coupling element, and a leakage compensation element. The buffer amplifier has an input coupled to a sense node, and an output. The link coupling element has an input coupled to the output of the buffer amplifier, and an output, wherein the link coupling element is unidirectional in a direction from the input to the output thereof. The leakage compensation element has a first current terminal coupled to the sense node, a control terminal coupled to the output of the link coupling element, and a second current terminal coupled to a reference voltage terminal.

Certain aspects of the present disclosure generally relate to a differential amplifier implemented using a complementary metal-oxide-semiconductor (CMOS) structure. The differential amplifier generally includes a first pair of transistors and a second pair of transistors coupled to the first pair of transistors. The gates of the first pair of transistors and gates of the second pair of transistors may be coupled to respective differential input nodes of the differential amplifier, and drains of the first pair of transistors and drains of the second pair of transistors may be coupled to respective differential output nodes of the differential amplifier. In certain aspects, the differential amplifier may include a biasing transistor having a drain coupled to a source of a transistor of the first pair of transistors and having a gate coupled to a common-mode feedback (CMFB) path of the differential amplifier.

Certain aspects of the present disclosure generally relate to a differential amplifier implemented using a complementary metal-oxide-semiconductor (CMOS) structure. The differential amplifier generally includes a first pair of transistors and a second pair of transistors coupled to the first pair of transistors. The gates of the first pair of transistors and gates of the second pair of transistors may be coupled to respective differential input nodes of the differential amplifier, and drains of the first pair of transistors and drains of the second pair of transistors may be coupled to respective differential output nodes of the differential amplifier. In certain aspects, the differential amplifier may include a biasing transistor having a drain coupled to a source of a transistor of the first pair of transistors and having a gate coupled to a common-mode feedback (CMFB) path of the differential amplifier.

An apparatus, such as a coherent optical receiver, includes a trans-impedance amplifier (TIA) and a low dropout (LDO) voltage regulator circuit for providing a supply voltage to the TIA. The LDO circuit is configured to adjust the supply voltage responsive to a DC voltage at an output of the TIA. In some implementations the LDO circuit may provide only a fraction of a supply current to the TIA, with another fraction provided by a partial current replica source.

A high voltage noise reduction unit that includes (i) an input that is configured to receive a high voltage input signal (HVIS); (ii) a positive isolated supply unit that is configured to receive the HVIS and to output a positive supply signal that floats on the HVIS; (iii) a negative isolated supply unit that is configured to receive the HVIS and to output a negative supply signal that floats on the HVIS; (iv) a low pass filter that is configured to filter the HVIS to provide a filtered high voltage signal; and (v) an amplifier that is configured to receive the positive supply signal, to receive the negative supply signal, to receive the filtered high voltage signal and amplify the filtered high voltage signal to provide a high voltage output signal.

A power amplifier comprising a power stage comprises a voltage detection circuit configured to detect an output voltage of the power stage, a current detection circuit configured to detect an output current of the power stage, a control voltage generation circuit configured to generate a control voltage substantially proportional to the detected output voltage and the detected output current, and a control circuit configured to decrease an output power of the power stage when the control voltage exceeds a predetermined value.

A power amplifier comprising a power stage comprises a voltage detection circuit configured to detect an output voltage of the power stage, a current detection circuit configured to detect an output current of the power stage, a control voltage generation circuit configured to generate a control voltage substantially proportional to the detected output voltage and the detected output current, and a control circuit configured to decrease an output power of the power stage when the control voltage exceeds a predetermined value.