Disclosed embodiments include a method for reducing amplifier offset drift comprised of receiving a first differential input signal at a first transistor base terminal and a second differential input signal at a second transistor base terminal, coupling the collector of the first transistor to the emitter of a third transistor and the emitter of the second transistor to the emitter of a fourth transistor, then coupling the base of the third transistor to the base of the fourth transistor. The method is also comprised of coupling the collector of the fourth transistor to an output terminal, generating a temperature dependent error correction current to minimize the difference in the amount of current flowing through the third transistor and the amount of current flowing through the fourth transistor, then injecting the error correction current into the emitter terminal of at least one of either the third transistor or the fourth transistor.

Disclosed embodiments include a method for reducing amplifier offset drift comprised of receiving a first differential input signal at a first transistor base terminal and a second differential input signal at a second transistor base terminal, coupling the collector of the first transistor to the emitter of a third transistor and the emitter of the second transistor to the emitter of a fourth transistor, then coupling the base of the third transistor to the base of the fourth transistor. The method is also comprised of coupling the collector of the fourth transistor to an output terminal, generating a temperature dependent error correction current to minimize the difference in the amount of current flowing through the third transistor and the amount of current flowing through the fourth transistor, then injecting the error correction current into the emitter terminal of at least one of either the third transistor or the fourth transistor.

Disclosed is a high accurate measurement circuit, and the feature is using bias switching circuit for compensating front end offset, and the back end offset of amplifier is also cancelled. In the real measurement environment, offset exists in the amplifier of the measurement circuit has, and non-ideal effects also exist in the interface between measurement terminal and the measurement circuit, such as leakage current of chip package pins or mismatch of the circuit. The above non-ideal effects belong to front end offset and cannot be compensated by the prior arts. The disclosed structure uses the bias switch circuit and uses different switching method in the two measurement timings. By subtracting the measurement results for the two measurement timings, the front end offset is compensated, and the back end offset of the amplifier is also cancelled.

Disclosed is a high accurate measurement circuit, and the feature is using bias switching circuit for compensating front end offset, and the back end offset of amplifier is also cancelled. In the real measurement environment, offset exists in the amplifier of the measurement circuit has, and non-ideal effects also exist in the interface between measurement terminal and the measurement circuit, such as leakage current of chip package pins or mismatch of the circuit. The above non-ideal effects belong to front end offset and cannot be compensated by the prior arts. The disclosed structure uses the bias switch circuit and uses different switching method in the two measurement timings. By subtracting the measurement results for the two measurement timings, the front end offset is compensated, and the back end offset of the amplifier is also cancelled.

An input stage circuit for an operational amplifier includes first and second differential pairs connected in parallel between positive and negative input terminals. Each differential pair comprises a pair of transistors that are intentionally and systematically mismatched. The mismatching of each transistor pair creates a pre-trim input offset voltage for the circuit. However, a unique current is utilized to bias each of the first and second differential pairs. By adjusting the differential between the bias currents, a composite input offset voltage is created that combines with the pre-trim input offset voltage to yield a total input offset voltage for the circuit that approaches zero. Additionally, adjusting the differential between the bias currents simultaneously trims the temperature coefficient of the total input offset voltage to zero while using limited power and producing minimal noise.

Systems and methods reduce unwanted effects caused by mismatch in amplifier circuits having components that are trimmable during and post-production to minimize DC offset. Various embodiments of the invention trim out amplifier mismatch by determining trim codes for two or more phases of operation of an amplifier circuit and use those trim codes to determine a final trim code for use in regular operation.