Enhanced operational amplifier trim circuitry and techniques are presented herein. In one implementation, a circuit includes a reference circuit configured to produce a set of reference voltages, and a digital-to-analog conversion (DAC) circuit. The DAC circuit comprises a plurality of transistor pairs, where each pair among the plurality of transistor pairs is configured to provide portions of adjustment currents for an operational amplifier based at least on the set of reference voltages and sizing among transistors of each pair. The circuit also includes drain switching elements coupled to drain terminals of the transistors of each pair and configured to selectively couple one or more of the portions of the adjustment currents to the operational amplifier in accordance with digital trim codes.

Measurement of signal power for variable or time varying signals. A log-linear VGA coupled in a feedback configuration to a difference detector and an integrator, includes a set of amplifier cells selectable by a sliding current generator, producing a sum of outputs. Outputs of the sliding current generator include a first control current provided using a sum of amplified currents, a sequence of intermediate control currents, and a final control current provided using a sum of amplified currents. Control currents to be summed can be differentially amplified or attenuated; attenuators include capacitors to compensate for capacitive loading. Selectable amplifier cells are differentially amplified or attenuated. Isolating switches and canceling stages reduce the effects of leakage between adjacent amplifier cells. The sliding current generator can have boosted current to first and last amplifier cells, providing a more linear-in-dB gain near a relative maximum or minimum.

Enhanced operational amplifier trim circuitry and techniques are presented herein. In one implementation, a circuit includes a reference circuit configured to produce a set of reference voltages, and a digital-to-analog conversion (DAC) circuit. The DAC circuit comprises a plurality of transistor pairs, where each pair among the plurality of transistor pairs is configured to provide portions of adjustment currents for an operational amplifier based at least on the set of reference voltages and sizing among transistors of each pair. The circuit also includes drain switching elements coupled to drain terminals of the transistors of each pair and configured to selectively couple one or more of the portions of the adjustment currents to the operational amplifier in accordance with digital trim codes.

A system that utilizes an amplified signal is disclosed that includes a plurality of first switches coupled to a plurality of first impedances. A plurality of second switches coupled to a plurality of second impedances. An amplifier having a first input coupled to the plurality of first switches and a second input coupled to the plurality of second switches. A leakage current offset source coupled to the first input of the amplifier, wherein the leakage current offset source cancels a leakage current component of a first current provided from the plurality of first switches to the first input.

A first amplifier circuit includes differential pair transistors that amplify a difference between input voltages and active load transistors connected to the differential pair transistors. A second amplifier circuit amplifies output voltage of the first amplifier circuit. An offset correction current source is connected in parallel with the active load transistors and adjusts electric current flowing through the differential pair transistors to correct offset voltage. An offset correction switch switches a driving state of the offset correction current source. A transconductance proportional current generation circuit generates transconductance proportional current for compensating for temperature drift of offset correction voltage for correcting the offset voltage. The transconductance proportional current is proportional to trans conductance.

An integrated circuit (IC) includes first, second, third, and fourth transistors, first and second current source devices, and a trim circuit. The first transistor has a first control input and a first current terminal. The second transistor has a second control input and a second current terminal. The third transistor had a third control input and third and fourth current terminals. The fourth transistor has a fourth control input and fifth and sixth current terminals. The first current source is coupled between a first power supply node and the third current terminal. The second current source is coupled between the first supply node and the fifth current terminal. The trim circuit is coupled between the fourth current terminal and a second power supply node, and is coupled between the sixth current terminal and the second power supply node. The trim circuit includes a resistive digital-to-analog converter (RDAC) circuit.

A first correction voltage generation circuit provides a first positive or negative correction voltage for correcting an input voltage. A second correction voltage generation circuit provides a second correction voltage identical in polarity to the first correction voltage in accordance with the first correction voltage. The second correction voltage is generated to have a temperature coefficient reverse in polarity to a temperature coefficient of the first correction voltage.

A signal receiver circuit includes a first amplification circuit and an offset compensation circuit. The first amplification circuit generates a first amplified signal and a second amplified signal by amplifying an input signal and a reference voltage. The offset compensation circuit adjusts voltage levels of the first and second amplified signals based on a DC level of the input signal and a voltage level of the reference voltage.

A first correction voltage generation circuit provides a first positive or negative correction voltage for correcting an input voltage. A second correction voltage generation circuit provides a second correction voltage identical in polarity to the first correction voltage in accordance with the first correction voltage. The second correction voltage is generated to have a temperature coefficient reverse in polarity to a temperature coefficient of the first correction voltage.

Enhanced operational amplifier trim circuitry and techniques are presented herein. In one implementation, a circuit includes a reference circuit configured to produce a set of reference voltages, and a digital-to-analog conversion (DAC) circuit. The DAC circuit comprises a plurality of transistor pairs, where each pair among the plurality of transistor pairs is configured to provide portions of adjustment currents for an operational amplifier based at least on the set of reference voltages and sizing among transistors of each pair. The circuit also includes drain switching elements coupled to drain terminals of the transistors of each pair and configured to selectively couple one or more of the portions of the adjustment currents to the operational amplifier in accordance with digital trim codes.