An offset-cancellation circuit having a first amplification stage with a gain of the first amplification stage and configured to receive an offset voltage of a first amplifier. A storage element is configured to be coupled to and decoupled from the first amplification stage and configured to store a potential difference output by the first amplification stage. The potential difference is determined by the offset voltage of the first amplifier and the gain of the first amplification stage. A second amplification stage is coupled to the storage element and configured to receive the potential difference from the storage element when the storage element is decoupled from the first amplification stage and configured to deliver an offset-cancellation current. The offset-cancellation current is determined by the potential difference and a gain of the second amplification stage.

A signal processing circuit. In some embodiments, the signal processing circuit includes a first sample and hold circuit and a second sample and hold circuit. The first sample and hold circuit may include: a hold capacitor; an input switch connected between a common input node and the hold capacitor; a signal path amplifier having an input connected to the hold capacitor; and an output switch connected between an output of the signal path amplifier and a common output node. An input of a voltage feedback amplifier may be connected to the hold capacitor, and an output of the voltage feedback amplifier may be operatively coupled to an internal node of the input switch.

A balanced differential transimpedance amplifier with a single-ended input operational over a wide variation in the dynamic range of input signals. A threshold circuit is employed to either or a combination of (1) generate a varying decision threshold to ensure a proper slicing over a wide range of input current signal levels; and (2) generate a bias current and voltage applied to an input of a transimpedance stage to cancel out a dependence of the transimpedance stage voltage input on input current signal levels.

Provided are an amplifier circuit capable of reducing DC offset voltage without an increase in chip area and degradation in frequency characteristics, and a multipath nested miller amplifier circuit. The amplifier circuit includes a chopper switching circuit, a sampling circuit configured to sample an output signal from the chopper switching circuit, and a holding circuit configured to hold a signal output from the sampling circuit.

Offset compensation circuitry for an amplification circuit. One example embodiment is a method of compensating a primary operational amplifier including: creating, by way of a companion circuit, a square wave having an amplitude, a period, and a direct current bias (DC bias), the amplitude proportional to an offset of the primary operational amplifier; integrating, by the companion circuit, the amplitude of the square wave for less than the period of the square wave, the integrating creates a compensation signal; and applying the compensation signal to the primary operational amplifier.

A device includes an amplifier and calibration circuitry coupled to the amplifier. The calibration circuitry is configured to receive calibration values. The calibration circuitry is also configured to generate an output value in response to receiving a timing input.

An apparatus of correcting an offset for a differential amplifier which compensates a direct current (DC) offset voltage in a differential analog signal amplifier using a resistive feedback structure to minimize a deviation and a method thereof are provided. The apparatus includes a differential amplifier that is configured to amplify a common DC voltage input via a first resistor and a second resistor with a predetermined amplification factor to output the amplified voltage. A controller is configured to compare voltages output from both output terminals of the differential amplifier to determine whether to generate an offset. In addition, the offset is corrected using a switching unit coupled in parallel to an input terminal of the differential amplifier in response to detecting a generated offset. The controller is also configured to adjust an asymmetric property of the input terminal of the differential amplifier to correct the generated offset.

Disclosed herein are a method, circuitry and an integrated circuit chip for use in signal processing. The integrated circuit chip comprises an operational amplifier, a reference amplifier, and a control unit. The control unit is coupled to the reference amplifier and to the operational amplifier. The control unit is configured to control the reference amplifier based on a signal received from the reference amplifier.

Offset compensation circuitry for an amplification circuit. One example embodiment is a method of compensating a primary operational amplifier including: creating, by way of a companion circuit, a square wave having an amplitude, a period, and a direct current bias (DC bias), the amplitude proportional to an offset of the primary operational amplifier; integrating, by the companion circuit, the amplitude of the square wave for less than the period of the square wave, the integrating creates a compensation signal; and applying the compensation signal to the primary operational amplifier.

The present disclosure relates to a device comprising two error amplifier stages having their first inputs interconnected, their second inputs interconnected and their outputs coupled to an output of the device, each stage comprising an operational amplifier; a circuit for calibrating the amplifier; a switch coupling an input of the amplifier to the first input; a switch coupling another input of the amplifier to the second input; a switch coupling an output of the amplifier to the stage output; a switch having on state which short-circuits the inputs of the amplifier; and a switch coupling the output of the amplifier to the calibration circuit.