H03H7/255

GAIN VARIATION COMPENSATION USING TEMPERATURE ATTENUATOR

Methods and apparatuses for signal attenuation is described. In an example, an attenuator can be configured to perform attenuation of signals for an integrated circuit. The attenuator can vary the attenuation with an ambient temperature. The attenuator can further adjust the attenuation based on a control signal applied to the attenuator. The control signal can be based on one or more of a temperature profile of the attenuator and a target gain variation of the integrated circuit.

DELAY CIRCUIT FOR TIME OFFSETTING A RADIOFREQUENCY SIGNAL AND INTERFERENCE REDUCING DEVICE USING SAID CIRCUIT
20170353203 · 2017-12-07 ·

A delay circuit for time offsetting an input radiofrequency signal, includes an all-pass filter having a given central frequency to linearize a phase-shift of an output signal relative to the input signal as a function of the frequency on a first frequency range; and first and second antiresonant circuits having respectively first and second central frequencies, the all-pass filter and the antiresonant circuits configured to linearize the phase-shift of the output signal relative to the input signal as a function of the frequency on a second frequency range including the first range. The difference between first and second central frequencies is less than 30% of the value of one of both frequencies, the difference between the first central frequency and the given central frequency of the all-pass filter is less than 30% of the value of a highest frequency between the first central frequency and the given central frequency.

ATTENUATION CIRCUIT

An attenuation circuit comprising: a connection-node for connecting to an RF connection; an isolation-capacitor connected in series between the connection-node and an internal-node; a first-bias-resistor connected in series between a first-control-node and the internal-node; a second-bias-resistor connected in series between the internal-node and a second-control-node; a first-attenuation-diode connected in series between the first-control-node and the internal-node, wherein the anode of the first-attenuation-diode is closest to the first-control-node; a second-attenuation-diode connected in series between the internal-node and the second-control-node, wherein the anode of the second-attenuation-diode is closest to the internal-node; a first-decoupling-capacitor connected in series between the first-control-node and the reference-node; and a second-decoupling-capacitor connected in series between the second-control-node and the reference-node.

VOLTAGE CONTROLLED EQUALIZER NETWORK
20170302254 · 2017-10-19 ·

An apparatus includes a radio frequency (RF) input port, an RF output port, a variable attenuation network, a first filter network, a second filter network, and a third filter network. The variable attenuation network may be coupled between the RF input port and the RF output port. Attenuation of the variable attenuation network is controlled by a first control signal and a second control signal. The first filter network may be connected between the RF input port and the RF output port. The second filter network may be connected between the variable attenuation network and a ground potential. The third filter network may be connected between the variable attenuation network and the ground potential. The first, the second, and the third filter networks modify performance of the variable attenuation network to produce a particular tilt of a radio frequency signal passing through the apparatus between the RF input port and the RF output port. The particular tilt is selectable by adjustment of at least one of the first and the second control signals.

High-power hybrid SPDT switch
11196453 · 2021-12-07 · ·

A switch assembly includes a PIN diode connected between an antenna port and a receive port, a first shunt FET device connected between the receive port and ground, a first series FET device connected between the antenna port and a transmit port, a second shunt FET device connected between the transmit port and ground, and a plurality of bias control contacts configured to receive a corresponding plurality of bias control voltages to forward bias the first shunt FET device and the first series FET device into an ON state and to reverse bias the PIN diode and the second shunt FET device into an OFF state in a transmit mode, and to reverse bias the first shunt FET device and the first series FET device into the OFF state and to forward bias the PIN diode and the second shunt FET device into the ON state in a receive mode.

SUBSTRATE INTEGRATED WAVEGUIDE SIGNAL LEVEL CONTROL ELEMENT AND SIGNAL PROCESSING CIRCUITRY

A signal level control element comprises a substrate having conductive formations defining a substrate integrated wave-guide arrangement disposed at least partly within the substrate; the substrate integrated waveguide arrangement providing a quadrature hybrid coupler having first and second pairs of signal ports, such that a signal introduced to a port of one pair of the first and second pairs is provided with equal amplitude but a 90 degree phase difference to both ports of the other pair of the first and second pairs; in which a port of the first pair is configured to receive an input signal and the other port of the first pair is configured to provide an output signal; and termination circuitry connected to the ports of the second pair, the termination circuitry providing, for each port of the second pair, a respective termination having a variable impedance dependent upon a respective control signal.

Filter for impedance matching

In one embodiment, an RF impedance matching network for a plasma chamber is disclosed. The matching network includes an electronically variable capacitor (EVC) comprising discrete capacitors, each discrete capacitor having a corresponding switching circuit for switching in and out the discrete capacitor to alter a total capacitance of the EVC. Each switching circuit includes a diode operably coupled to the discrete capacitor to cause the switching in and out of the discrete capacitor, and a filter circuit parallel to the diode, the filter comprising a filtering capacitor in series with an inductor.

HIGH-POWER HYBRID SPDT SWITCH
20210152208 · 2021-05-20 ·

A switch assembly includes a PIN diode connected between an antenna port and a receive port, a first shunt FET device connected between the receive port and ground, a first series FET device connected between the antenna port and a transmit port, a second shunt FET device connected between the transmit port and ground, and a plurality of bias control contacts configured to receive a corresponding plurality of bias control voltages to forward bias the first shunt FET device and the first series FET device into an ON state and to reverse bias the PIN diode and the second shunt FET device into an OFF state in a transmit mode, and to reverse bias the first shunt FET device and the first series FET device into the OFF state and to forward bias the PIN diode and the second shunt FET device into the ON state in a receive mode.

Absorptive phase invariant attenuator
10778191 · 2020-09-15 · ·

Methods and apparatus for an absorptive, phase invariant signal attenuator. In embodiments, PIN diodes can be coupled to a hybrid coupler. Incident power can be split by the coupler to a terminating resistor, a terminating diode, and a series diode. The terminating diode becomes increasingly well matched and absorptive over the attenuation range. The series diode becomes increasingly mismatched and reflective over the attenuation range. The terminating resistor increasingly absorbs incident power as the coupling value decreases due to increasing diode impedance over the attenuation range.

FILTER FOR IMPEDANCE MATCHING
20200126765 · 2020-04-23 ·

In one embodiment, an RF impedance matching network for a plasma chamber is disclosed. The matching network includes an electronically variable capacitor (EVC) comprising discrete capacitors, each discrete capacitor having a corresponding switching circuit for switching in and out the discrete capacitor to alter a total capacitance of the EVC. Each switching circuit includes a diode operably coupled to the discrete capacitor to cause the switching in and out of the discrete capacitor, and a filter circuit parallel to the diode, the filter comprising a filtering capacitor in series with an inductor.