Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C.sup.3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C.sup.3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C.sup.3MOS logic with low power conventional CMOS logic. The combined C.sup.3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

A clocked latch circuit includes an amplification circuit, a latch circuit, a first current source, and a second current source. The amplification circuit changes voltage levels of first and second output signals based on a clock signal, a first input signal, and a second input signal. The latch circuit maintains the voltage levels of the first and second output signals based on a complementary signal of the clock signal. The first current source allows a first current to flow to activate the amplification circuit. The second current source allows a second current that is different from the first current to flow to activate the latch circuit.

A D-type flip-flop (DFF) includes an input circuit having a plurality of transistors configured to receive a clock signal and a data signal, a first inverter (INV1) having a pair of transistors, the first inverter configured to receive an input voltage (x) from the input circuit at a first inverter input, the first inverter configured to provide an output voltage (y) to a first inverter output, a second inverter (INV2) coupled to the first inverter (INV1), the second inverter having a second inverter input and a second inverter output, the second inverter input coupled to the first inverter output, a third inverter (INV3) coupled to the second inverter (INV2), the third inverter having a third inverter input and a third inverter output, and a current device coupled to the first inverter output, the current device configured to provide a current at the first inverter output.

A D-type flip-flop (DFF) includes an input circuit having a plurality of transistors configured to receive a clock signal and a data signal, a first inverter (INV1) having a pair of transistors, the first inverter configured to receive an input voltage (x) from the input circuit at a first inverter input, the first inverter configured to provide an output voltage (y) to a first inverter output, a second inverter (INV2) coupled to the first inverter (INV1), the second inverter having a second inverter input and a second inverter output, the second inverter input coupled to the first inverter output, a third inverter (INV3) coupled to the second inverter (INV2), the third inverter having a third inverter input and a third inverter output, and a current device coupled to the first inverter output, the current device configured to provide a current at the first inverter output.

The present disclosure relates to a dynamic D flip-flop, a register, a chip, and a data processing apparatus. A dynamic D flip-flop is provided, including: an input terminal, configured to receive input data; an output terminal, configured to provide output data in response to the input data; clock signal terminal(s), configured to receive clock signal(s); a first latch unit, configured to latch the input data from the input terminal and transmit the input data under control of the clock signal(s); and a second latch unit, configured to latch data from the first latch unit and transmit the data latched by the first latch unit under control of the clock signal(s), where the first latch unit and the second latch unit are sequentially connected in series between the input terminal and the output terminal, and where the output terminal is configured to use data from the second latch unit as the output data for outputting.

In some examples, a level shifter circuit comprises: a first transistor pair cascoded at a first input node; a second transistor pair cascoded at a second input node, wherein the first and transistor pairs couple at a first node, a second node, a third node, and a fourth node; a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal; a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal; and a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node.

A signal receiving circuit includes a summing circuit, a clocked latch circuit and a feedback circuit. The summing circuit generates a summing signal based on an input signal and a feedback signal. The clocked latch circuit generates a sampling signal by sampling the summing signal in synchronization with a clock signal. The feedback circuit generates the feedback signal by selecting one among a plurality of coefficients based on the sampling signal.

In some examples, a level shifter circuit comprises: a first transistor pair cascoded at a first input node; a second transistor pair cascoded at a second input node, wherein the first and transistor pairs couple at a first node, a second node, a third node, and a fourth node; a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal; a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal; and a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node.

A semiconductor apparatus includes a pulse generation circuit which generates a pulse signal in response to a clock, and an amplification circuit which generates an output signal in response to an input signal, the clock, and the pulse signal, wherein the amplification circuit voltage is configured to amplify a voltage level difference between a pair of latch input nodes.

In some examples, a level shifter circuit comprises: a first transistor pair cascoded at a first input node; a second transistor pair cascoded at a second input node, wherein the first and transistor pairs couple at a first node, a second node, a third node, and a fourth node; a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal; a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal; and a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node.