A range sensor and a method thereof. The range sensor includes a light source configured to project a plurality of sheets of light at an angle within a field of view (FOV); an image sensor, wherein the image sensor is offset from the light source; collection optics; and a controller connected to the light source, the image sensor, and the collection optics, and configured to simultaneously determine a range of a distant object based on direct time-of-flight (TOF) and a range of a near object based on triangulation.

An integrated circuit includes a first time delay circuit, a second time delay circuit, and a master-slave flip-flop having a gated input circuit and a transmission gate. The first time delay circuit has a first input configured to receive a first clock signal and having a first output configured to generate a second clock signal. The second time delay circuit has a second input configured to receive the second clock signal and having a second output configured to generate a third clock signal. The transmission gate is configured to receive the first clock signal and the second clock signal to control a transmission state of the transmission gate. The gated input circuit is configured to have an input transmission state controlled by the third clock signal at the second output of the second time delay circuit.

A method of forming a semiconductor device includes forming active regions, forming S/D regions, forming MD contact structures and forming gate lines resulting in corresponding transistors that define a first time delay circuit having a first input configured to receive a first clock signal and having a first output configured to generate a second clock signal from the first clock signal; and corresponding transistors that define a second time delay circuit having a second input configured to receive the second clock signal and having a second output configured to generate a third clock signal from the first clock signal; forming a first gate via-connector in direct contact with the first gate line atop the first-type active region in the first area; and forming a second gate via-connector in direct contact with the second gate line atop the second-type active region in the second area.

Disclosed systems and methods relate to a power efficient voltage level translator. In a normal mode wherein a first supply voltage of the first voltage domain and a second supply voltage of the second voltage domain are different, the voltage level translator translates an input signal in a first voltage domain to an output signal in a second voltage domain In a bypass mode wherein the first supply voltage and the second supply voltage are substantially the same, a bypass circuit is configured to bypass the voltage level translator and provide the input signal as the output signal in the first voltage domain, thus avoiding delay introduced by the voltage level translator in the bypass mode. Further, a power-down circuit is configured to power-down the voltage level translator in the bypass mode but not in the normal mode.

Disclosed systems and methods relate to a power efficient voltage level translator. In a normal mode wherein a first supply voltage of the first voltage domain and a second supply voltage of the second voltage domain are different, the voltage level translator translates an input signal in a first voltage domain to an output signal in a second voltage domain. In a bypass mode wherein the first supply voltage and the second supply voltage are substantially the same, a bypass circuit is configured to bypass the voltage level translator and provide the input signal as the output signal in the first voltage domain, thus avoiding delay introduced by the voltage level translator in the bypass mode. Further, a power-down circuit is configured to power-down the voltage level translator in the bypass mode but not in the normal mode.

An integrated circuit includes a first time delay circuit, a second time delay circuit, and a master-slave flip-flop having a gated input circuit and a transmission gate. The first time delay circuit has a first input configured to receive a first clock signal and having a first output configured to generate a second clock signal. The second time delay circuit has a second input configured to receive the second clock signal and having a second output configured to generate a third clock signal. The transmission gate is configured to receive the first clock signal and the second clock signal to control a transmission state of the transmission gate. The gated input circuit is configured to have an input transmission state controlled by the third clock signal at the second output of the second time delay circuit.

A circuit includes a flip-flop included in a multi-stage shift register and a control element. The flip-flop includes an output field-effect transistor, a first field-effect transistor configured to operate to supply one of a high potential and a low potential to the gate of the output field-effect transistor, and a second field-effect transistor configured to operate to supply the other one of the high potential and the low potential to the gate of the output field-effect transistor. The control element is configured to operate to make an electric current flow between the gate and a power supply in the opposite direction of an off-leakage current from at least either one of the first field-effect transistor and the second field-effect transistor in a period where the first field-effect transistor and the second field-effect transistor are off.

A range sensor and a method thereof. The range sensor includes a light source configured to project a sheet of light at an angle within a field of view (FOV); an image sensor offset from the light source; collection optics; and a controller connected to the light source, the image sensor, and the collection optics, and configured to determine a range of a distant object based on direct time-of-flight and determine a range of a near object based on triangulation. The method includes projecting, by a light source, a sheet of light at an angle within an FOV; offsetting an image sensor from the light source; collecting, by collection optics, the sheet of light reflected off objects; and determining, by a controller connected to the light source, the image sensor, and the collection optics, a range of a distant object based on direct time-of-flight and a range of a near object based on triangulation simultaneously.

A range sensor and a method thereof. The range sensor includes a light source configured to project a sheet of light at an angle within a field of view (FOV); an image sensor offset from the light source; collection optics; and a controller connected to the light source, the image sensor, and the collection optics, and configured to determine a range of a distant object based on direct time-of-flight and determine a range of a near object based on triangulation. The method includes projecting, by a light source, a sheet of light at an angle within an FOV; offsetting an image sensor from the light source; collecting, by collection optics, the sheet of light reflected off objects; and determining, by a controller connected to the light source, the image sensor, and the collection optics, a range of a distant object based on direct time-of-flight and a range of a near object based on triangulation simultaneously.

A memory device includes a data receiver, a latch driver, and a voltage level shifter. The data receiver works in a first voltage, receives an enable signal, a reference signal, and an input data signal, and outputs an internal data signal by the first voltage. The latch driver receives a write select signal and the internal data signal, latches the internal data signal by the first voltage, and outputs at least one latch data signal by a second voltage. The voltage level shifter receives the at least one latch data signal by the second voltage and generates at least one output data signal by the at least one latch data signal. The voltage level shifter sets a voltage value of the at least one output data signal by the first voltage. The voltage value of the first voltage is greater than the voltage value of the second voltage.