An apparatus includes a sampling circuit, a sense circuit, and a tuning circuit. The sampling circuit samples an input signal according to a sampling clock signal to produce a sampled signal. The sense circuit determines a scaling factor based on a distortion in the sampled signal caused by the sampling clock signal. The tuning circuit generates an offset signal based on the sampling clock signal and the scaling factor. The offset signal reduces the distortion in the sampled signal caused by the sampling clock signal.

A phase correcting device includes a local oscillator that includes an all digital phase-locked loop configured to output a local oscillation signal, a first phase detector configured to detect a phase of the local oscillation signal to output the phase of the local oscillation signal, a reference phase device configured to generate a quasi-reference phase corresponding to a reference phase of the local oscillation signal to output the quasi-reference phase, based on a reference clock, a second phase detector configured to detect a fluctuation amount of a phase of the local oscillator, based on the phase detected by the first phase detector and the quasi-reference phase, and a correction circuit configured to correct the phase of the inputted signal by using a detection result of the second phase detector.

An apparatus includes a sampling circuit, a sense circuit, and a tuning circuit. The sampling circuit samples an input signal according to a sampling clock signal to produce a sampled signal. The sense circuit determines a scaling factor based on a distortion in the sampled signal caused by the sampling clock signal. The tuning circuit generates an offset signal based on the sampling clock signal and the scaling factor. The offset signal reduces the distortion in the sampled signal caused by the sampling clock signal.

A circuit includes an RF oscillator coupled in a phase-locked loop. The phase-locked loop is configured to receive a digital input signal, which is a sequence of digital words, and to generate a feedback signal for the RF oscillator based on the digital input signal. The circuit further includes a digital-to-analog conversion unit that includes a pre-processing stage configured to pre-process the sequence of digital words and a digital-to-analog-converter configured to convert the pre-processed sequence of digital words into the analog output signal. The circuit includes circuitry configured to combine the analog output signal and the feedback signal to generate a control signal for the RF oscillator. The pre-processing stage includes a word-length adaption unit configured to reduce the word-lengths of the digital words and a sigma-delta modulator coupled to the word-length adaption unit downstream thereof and configured to modulate the sequence of digital words having reduced word-lengths.

The present invention is related to a clock generating device for generating an internal clock signal having a frequency correlated with a clock frequency of an external oscillator when the clock frequency of the external oscillator is not specified in advance. A clock generating device 105 comprises a memory 134 and a PLL circuit 120. The memory 134 is configured to store information about a frequency of an external clock signal generated by an external oscillator 200 at a predetermined timing. The PLL circuit 120 generates a second clock signal correlated with a first clock signal based on the information stored in the memory 134.

A phase correcting device includes a local oscillator that includes an all digital phase-locked loop configured to output a local oscillation signal, a first phase detector configured to detect a phase of the local oscillation signal to output the phase of the local oscillation signal, a reference phase device configured to generate a quasi-reference phase corresponding to a reference phase of the local oscillation signal to output the quasi-reference phase, based on a reference clock, a second phase detector configured to detect a fluctuation amount of a phase of the local oscillator, based on the phase detected by the first phase detector and the quasi-reference phase, and a correction circuit configured to correct the phase of the inputted signal by using a detection result of the second phase detector.

When digital input data disappear temporarily, within a counting period of the counter and pulse generator, an output voltage of the voltage generator rises, a threshold detector compares the output voltage of the voltage generator with a plurality of threshold values to generate a plurality of comparison results, and a logic gate unit generates a control signal according to the comparison results, to a charge pump, so that the charge pump controls the voltage-controlled oscillator to accelerate or decelerate.

Techniques for reliable clock speed change and associated circuits and methods are disclosed. Internal voltage supplies of semiconductor devices may include oscillators and charge pump circuits. The oscillator may include at least two clock paths for generating clock signals having different clock frequencies, which can be provided to the charge pump circuit. Further, the oscillator may generate a reset signal configured to activate one clock path over the other (e.g., changing clock speeds). In some embodiments, the oscillator includes a flip-flop to align the reset signal with respect to an edge of an input clock signal supplied to the oscillator such that unintentional (undesired, unexpected) features in the output signal of the oscillator can be avoided when the oscillator changes clock speeds.

A phase correcting device includes a local oscillator configured to give a local oscillation signal to a device configured to detect a phase of an inputted signal, a first phase detector configured to detect a phase of the local oscillation signal to output the phase of the local oscillation signal, a reference phase device configured to generate a quasi-reference phase corresponding to a reference phase of the local oscillation signal at a time of an initial setting of the local oscillator to output the quasi-reference phase, based on a reference clock, a second phase detector configured to detect, a fluctuation amount of a phase of the local oscillator, based on the phase detected by the first phase detector and the quasi-reference phase, and a correction circuit configured to correct the phase of the inputted signal by using a detection result of the second phase detector.

A phase correcting device includes a local oscillator configured to give a local oscillation signal to a device configured to detect a phase of an inputted signal, a first phase detector configured to detect a phase of the local oscillation signal to output the phase of the local oscillation signal, a reference phase device configured to generate a quasi-reference phase corresponding to a reference phase of the local oscillation signal at a time of an initial setting of the local oscillator to output the quasi-reference phase, based on a reference clock, a second phase detector configured to detect, a fluctuation amount of a phase of the local oscillator, based on the phase detected by the first phase detector and the quasi-reference phase, and a correction circuit configured to correct the phase of the inputted signal by using a detection result of the second phase detector.