A test and measurement instrument includes a first data channel including a first data converter operating at a first rate, and a second data channel including a second data converter operating at a second rate that is different than the first rate. Rate controls may include a clock generation circuit. The clock generation circuit includes an intermediate frequency generator structured to generate an intermediate frequency clock from a first clock reference signal, a first frequency clock generator structured to generate a first frequency clock directly from the intermediate frequency clock, and a second frequency clock generator structured to generate a second frequency clock directly from the intermediate frequency clock. The first frequency clock may be used to control the rate of the first data channel, and the second frequency clock may be used to control the rate of the second data channel. Methods are also described.

An apparatus includes a digitally controlled oscillator (DCO), which includes an inductor coupled in series with a first capacitor. The DCO further includes a second capacitor coupled in parallel with the series-coupled inductor and first capacitor, a first inverter coupled in parallel with the second capacitor, and a second inverter coupled back-to-back to the first inverter. The DCO further includes a digital-to-analog-converter (DAC) to vary a capacitance of the first capacitor.

A method for checking a message in a communication system, in which multiple users are connected to a communication medium that includes two signal lines and exchange messages via same. A time difference between points in time of reception of a message that is sent on the communication medium is ascertained at two different, predefined positions on the communication medium, and based on a comparison of the time difference to at least one reference time difference, it is determined whether the message originates from a verified user. During the ascertainment of the time difference at the two positions, in each case a difference signal is formed from signals that have resulted on the two signal lines due to the message.

Both before and after a surprise clock stop, the apparatus and method of various embodiments supplies a stable and continuous clock to a memory module with a unique arrangement of circuit components, including a clock detector circuit, a clock-smoothing circuit, and one or more PLLs. Upon detection of a stopped host clock, a first PLL seamlessly switches to an alternate reference clock from an on-board crystal oscillator. A clock smoothing circuit allows the first PLL to maintain a steady phase and frequency without inducing glitches or period excursions greater than the natural jitter of the locked PLL; one or more optional downstream PLLs may drive additional clock domains.

A method for checking a message in a communication system, in which multiple users are connected to a communication medium that includes two signal lines and exchange messages via same. A time difference between points in time of reception of a message that is sent on the communication medium is ascertained at two different, predefined positions on the communication medium, and based on a comparison of the time difference to at least one reference time difference, it is determined whether the message originates from a verified user. During the ascertainment of the time difference at the two positions, in each case a difference signal is formed from signals that have resulted on the two signal lines due to the message.

Provided are a random number generating device and a method of operating the same. The random number generating device includes a source detector, a pulse generator, a counter, and a verification circuit. The source detector detects particles emitted from a source to generate a detection signal. The pulse generator generates pulses corresponding to the detected particles, based on the detection signal. The counter measures time intervals among the pulses and generates binary count values respectively corresponding to the time intervals. The verification circuit determines an output of the binary count values, based on the number of 0 values and the number of 1 values included in the binary count values.

An apparatus includes a digitally controlled oscillator (DCO), which includes an inductor coupled in series with a first capacitor. The DCO further includes a second capacitor coupled in parallel with the series-coupled inductor and first capacitor, a first inverter coupled in parallel with the second capacitor, and a second inverter coupled back-to-back to the first inverter. The DCO further includes a digital-to-analog-converter (DAC) to vary a capacitance of the first capacitor.

An apparatus includes a digitally controlled oscillator (DCO), which includes an inductor coupled in series with a first capacitor. The DCO further includes a second capacitor coupled in parallel with the series-coupled inductor and first capacitor, a first inverter coupled in parallel with the second capacitor, and a second inverter coupled back-to-back to the first inverter. The DCO further includes a digital-to-analog-converter (DAC) to vary a capacitance of the first capacitor.

An apparatus includes a digitally controlled oscillator (DCO), which includes an inductor coupled in series with a first capacitor. The DCO further includes a second capacitor coupled in parallel with the series-coupled inductor and first capacitor, a first inverter coupled in parallel with the second capacitor, and a second inverter coupled back-to-back to the first inverter. The DCO further includes a digital-to-analog-converter (DAC) to vary a capacitance of the first capacitor.

The application discloses a time-to-digital conversion circuit (100) including a first oscillator (110), a second oscillator (120), a first counting circuit (130), a second counting circuit (140), a first conversion circuit (150) and a processing circuit (160). The first oscillator is activated by a first signal and includes oscillating units having a first delay amount, wherein the first counting circuit is configured to count a number of times that the first tail end output signal of the first oscillator changes and store the same as a first counting result; the second counting circuit counts a number of oscillating units with an output change, other than the first tail end oscillating unit and stores the same as a second counting result; the first conversion circuit generates a first conversion signal according to the first counting result and the second counting result; the processing circuit generates the output signal at least according to the first conversion signal.