Provided are a Time-Interleaved Successive Approximation Register Analog-to-Digital Converter, TISAR ADC, and a calibration method thereof. The calibration method for the TISAR ADC may include: sampling an analog signal input into the TISAR ADC to generate a reference digital signal (S130); according to the reference digital signal and output digital signals generated by analog-to-digital conversion sub-modules of the TISAR ADC, obtaining capacitor array calibration parameters and time delay calibration parameters of the analog-to-digital conversion sub-modules; adjusting capacitor arrays of the corresponding analog-to-digital conversion sub-modules according to the capacitor array calibration parameters, respectively; and adjusting time delays of the corresponding analog-to-digital conversion sub-modules according to the time delay calibration parameters, respectively.

The disclosure discloses a temperature compensation circuit and method for a neural network computing-in-memory array. Reference arrays sparsely inserted in the computing-in-memory array are adopted to provide a reference voltage for ADCs, so that an input voltage and a reference voltage of the ADCs have a same temperature coefficient. Finally, after analog-to-digital conversion by the ADC, the digital output of the ADC is not affected by the external temperature, thereby ensuring the operational precision of the neural network. According to the temperature compensation circuit of the disclosure, the reference arrays have the same structure as the computing-in-memory array. The insertion density of the reference arrays is related to the temperature field where the computing-in-memory arrays are located. One reference array may provide the reference voltage of the ADC for a plurality of computing-in-memory arrays, thereby minimizing the increase of area and power consumption caused by inserting the reference arrays.

A system includes a digital-to-analog converter comprising a plurality of unit elements, and a dynamic element matching encoder coupled to the digital-to-analog converter. The dynamic element matching encoder includes a circuit configured to determine a number of unit elements of a digital-to-analog converter to be transitioned (N.sub.tm), determine a first number of unit elements to be turned on, and determine a second number of unit elements to be turned off. The circuit may further generate a first signal identifying individual unit elements of one or more unit elements of the digital-to-analog converter in the off state to be turned on, and a second signal identifying the individual unit elements of one or more unit elements of the digital-to-analog converter in the on state to be turned off.

Circuitry is disclosed herein that dynamically (temperature-invariant and voltage-invariant) adjusts the Ron of switches in a resistive Nyquist-rate digital to analog converter (DAC) to thereby reduce DAC nonlinearity errors and improve INL results of greater than 16b. Consistent with the present disclosure, the DAC includes an R-2R ladder in which each bit corresponds to a switch. A control circuit is provided for generating signals applied to the gate of the switch to cause the on-resistances of the switch to be a particular value, such that the on-resistance of the switch plus the sum of two resistors, one having the resistance R, and the other having a resistance R′ is equivalent to the resistance of the 2R-size resistors or twice the resistance of the R-sized resistors in the ladder.

A current steering digital-to-analog converter includes a plurality of current cells each including a current source circuit and a current switch circuit to selectively output a current in response to a first input signal corresponding to a digital signal; a dummy current cell including a dummy current source circuit and a dummy current switch circuit to output a current in response to a second input signal; and a current switch bias circuit coupled to the dummy current cell to track a first voltage of an internal node of the dummy current source circuit and configured to generate a first bias voltage applied to the current switch circuit.

This description relates generally to piecewise temperature compensation. In an example, a circuit includes a knee code selector that can be configured to set a knee point temperature for a correction current responsive to a respective knee point temperature code of knee point temperature codes and a respective temperature sense signal of temperature sense signals. The circuit includes an output circuit that can be configured to provide the correction current responsive to the respective temperature sense signal and temperature voltages, and a trim digital to analog converter (DAC) that can be configured to provide a piecewise compensation current responsive to the correction current and a respective trim code of trim codes.

In an embodiment a semiconductor device includes a first diode and a second diode of specified sizing or biasing ratio, a negative voltage supply, a first resistor for a proportional to absolute temperature (PTAT) voltage drop, wherein the first diode is connected between the negative supply voltage and the first resistor, an array of dynamically matched current sources employing a dynamic element matching controller, wherein the first resistor is connected between the first diode and a first input of the array, and wherein the second diode is connected between the negative supply voltage and a second input of the array and a successive approximation register (SAR) feedback loop configured to drive a voltage difference to zero, wherein the voltage difference occurs between a first node present between the first resistor and the first input of the array and a second node present between the second diode and the second input of the array.

A temperature stabilization technique for a digital-to-analog converter (DAC). The DAC is kept operating while a load, for example an analog computer, is disconnected from the DAC in order to reduce temperature changes that otherwise occur when the DAC is idle. The DAC may be supplied with adjusted input to compensate for changes in dissipation caused by the removal of the load.

In accordance with an embodiment, a digital-to-analog converter (DAC) includes: a W-2W current mirror that includes a first plurality of MOS transistors having a first width, and second plurality of MOS transistors having a second width that is twice the first width, where ones of the second plurality of MOS transistors are coupled between drains of adjacent ones of the first plurality of MOS transistors; and a bulk bias generator having a plurality of output nodes coupled to corresponding bulk nodes of the first plurality of MOS transistors, wherein the plurality of output nodes are configured to provide voltages that are inversely proportional to temperature.

Methods and devices are provided for circuits. One device includes an adjustment circuit having an adjustable resistor for modifying a resistance value of a resistive device, the adjustment circuit connected to an adjustment terminal of the resistive device. The resistance value of the adjustable resistor changes, when a voltage or charge on the adjustment terminal of the adjustable resistor is changed. The adjustable resistor is a phase change element with an adjusting terminal to which different voltage values are applied for adjusting a conversion device threshold value.