Technologies relating to implementing two-stage ramp ADCs in crossbar array circuits for high performance matrix multiplication are disclosed. An example two-stage ramp ADC includes: a transimpedance amplifier configured to convert an input signal from current to voltage; a comparator connected to the transimpedance amplifier; a switch bias set connected to the comparator; a switch side capacitor in parallel with the switch bias set; a ramp side capacitor in parallel with the switch bias set; a ramp generator connected to the comparator via the ramp side capacitor, wherein the ramp generator is configured to generate a ramp signal; a counter; and a memory connected to the comparator, wherein the memory is configured to store an output of the comparator.

An integrator and an analog-to-digital converter are provided. The analog-to-digital converter includes the integrator, a comparison circuit and a control logic circuit. The integrator includes an operational amplifier, offset capacitors, input capacitors, integral capacitors and controllable switches. The input capacitors and the integral capacitors are connected to the operational amplifier via controllable switches, so that the integrator operates in various operation modes. Operation states of the offset capacitors in a first phase and a second phase of an operation cycle are controlled by switching on or off the controllable switches. Therefore, an offset voltage of the integrator is eliminated, and conversion efficiency and conversion accuracy of the analog-to-digital converter is improved.

An analog-to-digital conversion circuit includes a convertor configured to perform a first comparison operation for sensing a noise based on a reset signal and to perform a second comparison operation for sensing raw data to output data which is obtained by removing the noise from the raw data, and a ramp voltage generator configured to generate a ramp voltage used for the first comparison operation and the second comparison operation and to output the ramp voltage to the convertor. The ramp voltage generator includes a first current source for supplying a bias current for generating the ramp voltage in response to a first control signal, a second current source for supplying a boost current for generating the ramp voltage in response to a second control signal, and a generation circuit for generating the ramp voltage based on the bias current and the boost current.

A signal converting apparatus includes a comparing device, a first digital-slope quantizer, and a second digital-slope quantizer. The comparing device having a first input terminal and a second input terminal for receiving a first received signal and a second received signal, and for generating an output signal at an output port. The first digital-slope quantizer generates a first set of digital signals to monotonically adjust the first received signal and the second received signal at the first input terminal and the second input terminal during a first phase according to a first quantization unit. The second digital-slope quantizer generates a second set of digital signals to monotonically adjust the first received signal and the second received signal at the first input terminal and the second input terminal during a second phase after the first phase according to a second quantization unit.

The present invention pertains to a high-speed successive approximation analog-to-digital converter of two bits per circle, includes three switches, two capacitor arrays, three comparators, an encoding circuit, a first switch array corresponding to the first capacitor array, a second switch array corresponding to the second capacitor array, a shifting register and a digital correction unit. The analog-to-digital converter, featuring doubled speed, realizes a successive approximation process without any fault when a high-bit large capacitor is unsettled. Thus no redundancy bit capacitor is required to compensate for unsettled pre-stage large capacitor. By using the encoding circuit, a thermometer code is converted into a binary code effectively, and inherent errors of comparators are reduced by the randomization of three comparators.

A cyclic analog to digital converter for digitizing an output from a photoplethysmography sensor has a buffer amplifier for setting a voltage of the feedback capacitance. Additionally, digital averaging circuit is preferably provided for averaging the digital output from the cyclic analog to digital converter for the several conversions. Finally, voting logic is additionally provided for declaring the digital bits based on successive comparisons by the one or more comparators.

The amplifier load current cancellation in a current integrator comprises applying an input current to an operational transconductance amplifier provided with an integration capacitor for current integration, leading an output current of the operational transconductance amplifier through a sensing resistor, thus producing a voltage drop over the sensing resistor, generating a cancellation current dependent on the voltage drop over the sensing resistor, and injecting the cancellation current to the output current, before or after the output current passes the sensing resistor, thus eliminating a dependence of the output current on the input current.

A circuit configured to compute matrix multiply-and-add calculations that includes a digital-to-time converter configured to receive a digital input and output a signal proportional to the digital input and modulated in time-domain associated with a reference time, a memory including a crossbar network, wherein the memory is configured to receive the time modulated signal from the digital-to-time converter and output a weighted signal scaled in response to network weights of the crossbar network and the time modulated input signal, and an output interface in communication with the crossbar network and configured to receive its weighted output signal and output a digital value proportional to at least the reference time using a time-to-digital converter.

An integrator and an analog-to-digital converter are provided. The analog-to-digital converter includes the integrator, a comparison circuit and a control logic circuit. The integrator includes an operational amplifier, offset capacitors, input capacitors, integral capacitors and controllable switches. The input capacitors and the integral capacitors are connected to the operational amplifier via controllable switches, so that the integrator operates in various operation modes. Operation states of the offset capacitors in a first phase and a second phase of an operation cycle are controlled by switching on or off the controllable switches. Therefore, an offset voltage of the integrator is eliminated, and conversion efficiency and conversion accuracy of the analog-to-digital converter is improved.

A signal converting apparatus includes a comparing device, a first digital-slope quantizer, and a second digital-slope quantizer. The comparing device having a first input terminal and a second input terminal for receiving a first received signal and a second received signal, and for generating an output signal at an output port. The first digital-slope quantizer generates a first set of digital signals to monotonically adjust the first received signal and the second received signal at the first input terminal and the second input terminal during a first phase according to a first quantization unit. The second digital-slope quantizer generates a second set of digital signals to monotonically adjust the first received signal and the second received signal at the first input terminal and the second input terminal during a second phase after the first phase according to a second quantization unit.