An apparatus configured to convert an analog input signal into a digital output signal may include a first amplification circuit configured to receive the analog input signal and a plurality of reference voltages and amplify differences between the analog input signal and the plurality of reference voltages; a plurality of first capacitors configured to respectively store charges corresponding to signals outputted by the first amplification circuit; a second amplification circuit configured to amplify differences among voltages of the plurality of first capacitors; a plurality of second capacitors configured to respectively store charges corresponding to signals outputted by the second amplification circuit; and a comparison circuit configured to generate the digital output signal by comparing voltages of the plurality of second capacitors with each other.

An analog-to-digital converting system and a method with offset correction mechanisms are provided. The method includes steps of: obtaining a direct current offset of an output voltage of a digital analog conversion unit in a system; obtaining first capacitance weights and second capacitance weights sequentially from small to large; subtracting the direct current offset from a digital signal; and multiplying bit values of the digital signal respectively by the corresponding first capacitance weight value or second capacitance weight value to output a decode signal.

Single-stage and multiple-stage current-mode Analog-to-Digital converters (iADC)s utilizing apparatuses, circuits, and methods are described in this disclosure. The disclosed iADCs can operate asynchronously and be free from the digital clock noise, which also lowers dynamic power consumption, and reduces circuitry overhead associated with free running clocks. For their pseudo-flash operations, the disclosed iADCs do not require their input current signals to be replicated which saves area, lowers power consumption, and improves accuracy. Moreover, the disclosed methods of multi-staging of iADCs increase their resolutions while keeping current consumption and die size (cost) low. The iADC's asynchronous topology facilitates decoupling analog-computations from digital-computations, which helps reduce glitch, and facilitates gradual degradation (instead of an abrupt drop) of iADC's accuracy with increased input current signal frequency. The iADCs can be arranged with minimal digital circuitry (i.e., be digital-light), thereby saving on die size and dynamic power consumption.

An apparatus configured to convert an analog input signal into a digital output signal may include a first amplification circuit configured to receive the analog input signal and a plurality of reference voltages and amplify differences between the analog input signal and the plurality of reference voltages; a plurality of first capacitors configured to respectively store charges corresponding to signals outputted by the first amplification circuit; a second amplification circuit configured to amplify differences among voltages of the plurality of first capacitors; a plurality of second capacitors configured to respectively store charges corresponding to signals outputted by the second amplification circuit; and a comparison circuit configured to generate the digital output signal by comparing voltages of the plurality of second capacitors with each other.