Techniques for interpolating two voltages without loading them and without requiring significant power or additional area are described. The techniques include specific topologies for the buffering amplifiers that offer accuracy by cancelling systematic error sources without relying on high gain, thus simplifying the frequency compensation, and reducing power consumption. This can be achieved by biasing the amplifiers from the load current by an innovative feedback structure, which can remove the need for high impedance nodes inside the amplifiers.

Techniques for interpolating two voltages without loading them and without requiring significant power or additional area are described. The techniques include specific topologies for the buffering amplifiers that offer accuracy by cancelling systematic error sources without relying on high gain, thus simplifying the frequency compensation, and reducing power consumption. This can be achieved by biasing the amplifiers from the load current by an innovative feedback structure, which can remove the need for high impedance nodes inside the amplifiers.

An arithmetic circuit includes an auto-zero amplification circuit that compensates an offset of an entered differential signal, and a comparator circuit that converts an output signal from the auto-zero amplification circuit to a digital signal. The auto-zero amplification circuit and comparator circuit are provided in the same package.

An encoder system includes a configurable detector array, wherein the configurable detector array includes a plurality of detectors. In an embodiment, the encoder system includes an application-specific integrated circuit (ASIC). The encoder system may also include a memory operable to store a partition map that defines a state for each of the plurality of detectors. In an embodiment, the memory includes a non-volatile memory. The encoder system may also include a controller, such as a microcontroller, operable to read from the memory the partition map and to adjust the partition map according to a misalignment measurement before configuring the configurable detector array. The encoder system may also include an emitter operable to generate a flux modulated by a motion object, wherein the configurable detector array is operable to receive the flux and generate respective current outputs for each of the detectors in response to the flux.

An encoder system includes a configurable detector array, wherein the configurable detector array includes a plurality of detectors. In an embodiment, the encoder system includes an application-specific integrated circuit (ASIC). The encoder system may also include a memory operable to store a partition map that defines a state for each of the plurality of detectors. In an embodiment, the memory includes a non-volatile memory. The encoder system may also include a controller, such as a microcontroller, operable to read from the memory the partition map and to adjust the partition map according to a misalignment measurement before configuring the configurable detector array. The encoder system may also include an emitter operable to generate a flux modulated by a motion object, wherein the configurable detector array is operable to receive the flux and generate respective current outputs for each of the detectors in response to the flux.

The present technology relates to an image sensor, an electronic apparatus, a comparator, and a drive method which enable achievement of a noise reduction while maintaining high speed of AD conversion. An ADC for performing AD conversion for an electrical signal output from a pixel includes a comparator that compares the electrical signal and a reference signal, a level of which is changed and a counter that counts time necessary for a change of the reference signal to a coincidence of the electrical signal and the reference signal on the basis of output signals from the comparator. The comparator includes a differential amplifier that outputs a comparison result signal indicating a comparison result obtained by comparing the electrical signal and the reference signal and a plurality of output amplifiers that outputs signals obtained by amplifying the comparison result signal output from the differential amplifier as the output signals at different timings. The present technology can be applied to, for example, an ADC that performs AD conversion for an electrical signal output from a pixel.

A reference voltage sub-system that allows fast power up after spending extended periods in an ultra-low power standby mode. The reference voltage sub-system includes a reference voltage buffer, a reference voltage keeper, an active calibration facility for selectively adjusting the reference voltage keeper output to match the reference voltage buffer output, and a selection means for selecting between the reference voltage buffer output and the reference voltage keeper output.

A reference voltage sub-system that allows fast power up after spending extended periods in an ultra-low power standby mode. The reference voltage sub-system includes a reference voltage buffer, a reference voltage keeper, an active calibration facility for selectively adjusting the reference voltage keeper output to match the reference voltage buffer output, and a selection means for selecting between the reference voltage buffer output and the reference voltage keeper output.

A flash analog to digital converter (ADC) includes a first, second, and third double data rate comparator core configured to determine a relative voltage of a first differential input signal during each of a rising edge and a falling edge in a single clock cycle of a comparator clock input to the comparator core. An inverted comparator clock coupled to the third comparator core reduces kickback noise. The ADC includes a first and a second floating voltage reference configured to shift a voltage of a differential comparator input by a fixed amount, and produce the first and second differential input signal. The third comparator core is cross coupled between the first and second comparator core.

A reference voltage sub-system that allows fast power up after spending extended periods in an ultra-low power standby mode. The reference voltage sub-system includes a reference voltage buffer, a reference voltage keeper, an active calibration facility for selectively adjusting the reference voltage keeper output to match the reference voltage buffer output, and a selection means for selecting between the reference voltage buffer output and the reference voltage keeper output.