An analog-to-digital converter (ADC) including: a signal input adapted to receive an analog signal; a first reference voltage input adapted to receive a first reference voltage; a second reference voltage input adapted to receive a second reference voltage, the second reference voltage is different than the first reference voltage; a first delay circuit having a first delay input coupled to the signal input, a second delay input coupled to the first reference voltage input, a first delay output and a second delay output; a second delay circuit having a third delay input coupled to the signal input, a fourth delay input coupled to the second reference voltage input; a third delay output and a fourth delay output; a first comparator having a first comparator input coupled to the first delay output, a second comparator input coupled to the second delay output and a first comparator output; and a second comparator having a third comparator input coupled to the third delay output, a fourth comparator input coupled to the fourth delay output and a second comparator output.

Methods and apparatus disclosed herein implement or otherwise embody a technique that compensates for cyclic position errors in encoder-based position detection, wherein the cyclic position errors arise from the presence of harmonic components in the encoder signals relied upon for position determination. Using position-domain compensation for errors arising in the encoder domain offers computational simplicity and impressive compensation performance, even when compensating for a plurality of higher harmonics in the encoder signals, e.g., third harmonic, fifth harmonic, etc. Consequently, even high-precision position monitoring or control can use relatively inexpensive types of encoders known to output encoder signals having significant harmonic components.

A method of constructing a waveform from N sampled data captured at N successive points in time, includes, in part, applying the N sampled data, K data at a time, to each of M delayed replicas of a filter that includes K taps so to generate N×M interpolated data. The waveform is then constructed from the N sampled data and the N×M interpolated data.

A method of constructing a waveform from N sampled data captured at N successive points in time, includes, in part, applying the N sampled data, K data at a time, to each of M delayed replicas of a filter that includes K taps so to generate N×M interpolated data. The waveform is then constructed from the N sampled data and the N×M interpolated data.

An analog-to-digital converter (ADC) including: a signal input adapted to receive an analog signal; a first reference voltage input adapted to receive a first reference voltage; a second reference voltage input adapted to receive a second reference voltage, the second reference voltage is different than the first reference voltage; a first delay circuit having a first delay input coupled to the signal input, a second delay input coupled to the first reference voltage input, a first delay output and a second delay output; a second delay circuit having a third delay input coupled to the signal input, a fourth delay input coupled to the second reference voltage input; a third delay output and a fourth delay output; a first comparator having a first comparator input coupled to the first delay output, a second comparator input coupled to the second delay output and a first comparator output; and a second comparator having a third comparator input coupled to the third delay output, a fourth comparator input coupled to the fourth delay output and a second comparator output.

A method of converting an analog signal to a digital code, comprising: using a first comparator to receive an input signal and a first comparison signal, and to generate a first output as a function of the input signal and the first comparison signal; using a second comparator to receive the input signal and a second comparison signal, and to generate a second output as a function of the input signal and the second comparison signal; and using an interpolation comparator to receive the first and second outputs, and to generate a third output based on relative timing of the first and second outputs; further including multiplexing to permit a second-level comparator to receive timing signals from the interpolation comparator and only one of two dummy comparators.

A method for providing back-compatibility for rational sampling rate disparities between two circuitries, comprises: a) providing a Phase Locked Loop (PLL) operating at a rate different than that of the Symbols generator, which is coupled to a Digital to Analog Converter (DAC) or an Analog to Digital Converter (ADC); b) providing an interpolation filter coupled to said converter, which filter is adapted to perform sampling rate conversion operations on the samples using zero-stuffing, filtering, and decimation, or the like computation-saving algorithm; and c) obtaining the sampling of the symbols at the required and compatible rate.

An interpolative divider divides an input clock signal according to a divide ratio and supplies an output clock signal. An integer divider receives the input clock signal and supplies an integer divider output signal. A phase interpolator is coupled to the integer divider and delays the integer divider output signal according to a quantization error. The phase interpolator includes first and second current sources. The first current source turns on k unit current elements during a first part of a charging cycle to charge a first capacitor to a first voltage, 0kM, k and M are integers, and k is determined by the digital quantization error. The second current source turns on k+M unit elements to charge a second capacitor during a second part of the charging cycle. The output clock signal transitions when the first voltage equals the second voltage.

A method of converting an analog signal to a digital code, comprising: using a first comparator to receive an input signal and a first comparison signal, and to generate a first output as a function of the input signal and the first comparison signal; using a second comparator to receive the input signal and a second comparison signal, and to generate a second output as a function of the input signal and the second comparison signal; and using an interpolation comparator to receive the first and second outputs, and to generate a third output based on relative timing of the first and second outputs; further including multiplexing to permit a second-level comparator to receive timing signals from the interpolation comparator and only one of two dummy comparators.

An analog-to-digital converter has first and second comparators and an interpolation comparator. The first comparator receives an input signal and a comparison signal, and generates an output as a function of the input signal and the comparison signal. The second comparator receives the input signal and a second comparison signal (different from the first comparison signal), and generates a second output as a function of the input signal and the second comparison signal. The interpolation comparator, operatively connected to the first and second comparators, receives the first and second outputs, and generates a third output based on relative timing of the first and second outputs.