A system and method for a frequency detector circuit includes: a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input; a first circuit configured to generate a second edge output; a second circuit configured to generate a third edge output; and a combinational logic configured to output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high and configured to output a DOWN output when the first edge output, the second edge output, and the third edge output are all low.

A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device waits for a synchronization point sequence. Upon detecting the synchronization point sequence, the second remote device implements a predetermined feature set and synchronizes itself to the state diagram at a common point as the host device and first remote device.

A clock and data recovery (CDR) system includes a correlator configured to receive data, determine a first value of the received data, and output a second value corresponding to the received data, an accumulator configured to generate an accumulation value by accumulating the second value output from the correlator and output the accumulation value, and a state machine configured to determine whether a repeating pattern is present in the CDR system based on the accumulation value.

A phase calibration method includes sweeping phase codes applicable to a serial clock signal, identifying a first, a second, a third, and a fourth phase code, wherein the first phase code causes zero plus a first threshold number of bits extracted from the serial data signal to be a particular value, wherein the second phase code causes all minus a second threshold number of bits extracted from the serial data signal to be the particular value, wherein the third phase code causes all minus a third threshold number of bits extracted from the serial data signal to be the particular value, wherein the fourth phase code causes zero plus a fourth threshold number of bits extracted from the serial data signal to be the particular value, determining an average phase code based on the identified phase codes.

Disclosed is a card clock recovery system for use in an NFC card transceiver couplable to an NFC reader. The card clock recovery system has: a phase lock loop having: a phase/frequency detector, which is configured to receive a reference signal provided at an RX port of a matching network during a receiving mode of the NFC transceiver or to receive a reference signal provided at the RX port of the matching network during a transmission mode of the NFC transceiver, to receive a loop feedback signal, and to provide a phase error signal that represents a phase difference between the reference signal and the loop feedback signal; a loop filter configured to receive a corrected phase error signal that is derived from the phase error signal, and to provide a filtered corrected phase error signal; a controllable oscillator, which is configured to receive the filtered corrected phase error signal and to provide a controlled frequency output signal, which is provided as the card clock generation control signal to a card clock generation unit of an NFC card transceiver, and as the loop feedback signal, via the loop feedback line, to the phase/frequency detector. The card clock recovery system further has a phase offset correction unit, which is configured to receive the phase error signal provided by the phase/frequency detector and to provide the corrected phase error signal to the loop filter, and which has a phase error sampling unit, a phase offset computation unit, and a phase subtractor unit.

An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data clock signals to note the locations of zero crossings for one or more selected data patterns. The pattern or patterns may be selected from among those apt to produce the greatest timing error. Equalization settings may then be adjusted to align the zero crossings of the selected data patterns with the recovered edge clock signal.

A method for recovering the symbol time by a receiver to decode a sequence of symbols transmitted by a transmitter when the symbol time of the transmitter is biased with respect to the symbol time of the receiver. When a transition is detected between two consecutive symbols, an absolute error on the instant of the current symbol is measured and a statistical model of the bias is updated. A correction may then be applied to the instants of the subsequent symbols depending on the measured absolute error and/or a bias estimated from the statistical model. During periods in which there are no transitions between symbols, an absolute error cannot be measured, but it is still possible to apply a correction to the instants of the subsequent symbols depending on a relative error extrapolated from the statistical model.

A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device waits for a synchronization point sequence. Upon detecting the synchronization point sequence, the second remote device implements a predetermined feature set and synchronizes itself to the state diagram at a common point as the host device and first remote device.

A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device waits for a synchronization point sequence. Upon detecting the synchronization point sequence, the second remote device implements a predetermined feature set and synchronizes itself to the state diagram at a common point as the host device and first remote device.

A transceiver includes a transmitter and a receiver which are connected to each other through a first line and a second line. The transmitter transmits a first clock training pattern to the receiver in a first period, transmits a second clock training pattern and a first first payload to the receiver in a second period, and transmits a third clock training pattern and a second first payload to the receiver in a third period. The first clock training pattern, the second clock training pattern, and the third clock training pattern are variable based on a plurality of driving modes.