Transmission of data over a serial link based on a unidirectional clock signal is provided. A unidirectional clock signal is generated based on a first clock of a master device. The unidirectional clock signal is sent to a slave device that is connected to the serial link. The master device transmits data to the slave device over the serial link based on the first clock. The slave device receives the unidirectional clock signal from a master device. The slave device transmits data over the serial link to the master device based on the unidirectional clock signal.

An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data clock signals to note the locations of zero crossings for one or more selected data patterns. The pattern or patterns may be selected from among those apt to produce the greatest timing error. Equalization settings may then be adjusted to align the zero crossings of the selected data patterns with the recovered edge clock signal.

A system and method for a frequency detector circuit includes: a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input; a first circuit configured to generate a second edge output; a second circuit configured to generate a third edge output; and a combinational logic configured to output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high and configured to output a DOWN output when the first edge output, the second edge output, and the third edge output are all low.

One aspect of the present invention includes a bi-phase communication receiver system. The system includes an analog-to-digital converter (ADC) configured to sample a bi-phase modulation signal to generate digital samples of the bi-phase modulation signal. The system also includes a bi-phase signal decoder configured to decode the bi-phase modulation signal based on the digital samples. The system further includes a preamble detector comprising a digital filter configured to evaluate the digital samples to generate an output and to detect a preamble of the bi-phase modulation signal for decoding the bi-phase modulation signal based on the output.

A user station for a bus system and a method for transmitting a message at different bit rates in a bus system is provided. The user station includes a communication control unit for creating a message for at least one further user station of the bus system. The communication control unit is designed to provide in the message a first phase to be transmitted at a first bit rate, and to provide a second phase to be transmitted at a second bit rate, which is faster or slower than the first bit rate. The communication control unit is designed to provide in the message between the first and second phase a predetermined bit pattern for a bit rate switchover between the first and second bit rate. The predetermined bit pattern includes, both before and after the bit rate switchover, a flank for synchronization.

A system for communicating data over a transmission line is disclosed. In one example implementation, the system may include a transmitter configured to modulate a control signal onto an RF signal using amplitude-shift keying modulation to generate a transmit signal. The system may include a receiver and a transmission line coupling the transmitter to the receiver. The transmitter may be configured to transmit the transmit signal over the transmission line to the receiver, and the receiver may be configured to de-modulate the control signal and extract clock information associated with the transmitter. In some embodiments, the system may include a tuning circuit and a modal antenna, and the tuning circuit may be or include the receiver. The receiver may be configured to adjust a mode of the modal antenna based on the control signal transmitted by the transmitter.

A user station for a bus system and a method for transmitting a message at different bit rates in a bus system is provided. The user station includes a communication control unit for creating a message for at least one further user station of the bus system. The communication control unit is designed to provide in the message a first phase to be transmitted at a first bit rate, and to provide a second phase to be transmitted at a second bit rate, which is faster or slower than the first bit rate. The communication control unit is designed to provide in the message between the first and second phase a predetermined bit pattern for a bit rate switchover between the first and second bit rate. The predetermined bit pattern includes, both before and after the bit rate switchover, a flank for synchronization.

A method of operating a digital radio receiver is provided as follows: a) receiving a radio signal comprising a symbol sequence; b) selecting a portion of the symbol sequence; c) determining a first error between the selected portion of the symbol sequence and a first predetermined symbol sequence using a difference metric; d) determining a set of second errors between the selected portion of the symbol sequence and a respective set of second predetermined symbol sequences, each formed by prepending different length portions of a predetermined preamble symbol sequence to a beginning of the first predetermined symbol sequence; and e) determining a minimum error from the first error and the set of second errors. If the first error is not the minimum error, a different portion of the symbol sequence is selected. Otherwise, a following portion of the symbol sequence is decoded to produce a data payload.

A transceiver device includes a transmitter and a receiver connected to each other through a first line and a second line. The transmitter transmits signals having a first voltage range to the first line and the second line in a first mode, and transmits signals having a second voltage range less than the first voltage range to the first line and the second line in a second mode. The transmitter encodes an original payload to generate a first payload in the second mode, and transmits a clock training pattern and the first payload through the first line and the second line. The receiver decodes the first payload and outputs reception data corresponding to the original payload in the second mode.

A system for communicating data over a transmission line is disclosed. In one example implementation, the system may include a transmitter configured to modulate a control signal onto an RF signal using amplitude-shift keying modulation to generate a transmit signal. The system may include a receiver and a transmission line coupling the transmitter to the receiver. The transmitter may be configured to transmit the transmit signal over the transmission line to the receiver, and the receiver may be configured to de-modulate the control signal and extract clock information associated with the transmitter. In some embodiments, the system may include a tuning circuit and a modal antenna, and the tuning circuit may be or include the receiver. The receiver may be configured to adjust a mode of the modal antenna based on the control signal transmitted by the transmitter.