Patent classifications
H05K2201/09518
CONNECTION STRUCTURE EMBEDDED SUBSTRATE
A connection structure embedded substrate includes a printed circuit board including a first insulating body and a plurality of first wiring layers disposed on at least one of an external region or an internal region of the first insulating body; and a connection structure embedded in the first insulating body and including first and second substrates. The first and second substrates are disposed adjacent to each other.
Method for producing a printed circuit board
A method for producing a printed circuit board is disclosed, In the method, a slot is formed in a substrate having at least three layers with the slot extending through at least two of the layers. The slot has a length and a width with the length being greater than the width. The sidewall of the substrate surrounding the slot is coated with a conductive layer. Then, the conductive layer is separated into at least two segments that are electrically isolated along the side wall of the substrate.
DISPLAY DEVICE
Provided is a display device including: a display panel in which a display area and a non-display area located around the display area are defined; an external device which is disposed on the non-display area of the display panel; and a cover member which is disposed on the external device, wherein the external device includes a driving chip and a printed circuit film which is disposed on the non-display area of the display panel and spaced apart from the display area with the driving chip interposed between the printed circuit film and the display area in plan view, and the cover member includes a first insulating tape disposed on the external device, a first conductive tape disposed on the first insulating tape and a second insulating tape disposed on the first conductive tape, wherein the second insulating tape includes an electrostatic induction opening penetrating the second insulating tape in a thickness direction, a planar size of the first conductive tape is greater than a planar size of the second insulating tape, the first conductive tape protrudes further toward the display area than the second insulating tape in plan view, and the electrostatic induction opening is disposed on a part of the first conductive tape which protrudes further toward the display area than the second insulating tape.
APPARATUS, SYSTEM, AND METHOD FOR MITIGATING THE SWISS CHEESE EFFECT IN HIGH-CURRENT CIRCUIT BOARDS
A disclosed apparatus may be a circuit board that includes (1) a first unique sublaminate that includes a plurality of ground layers and a plurality of signal layers, (2) a second unique sublaminate that includes a plurality of power layers and another plurality of signal layers, and (3) a symmetry axis that bisects the circuit board between the first unique sublaminate and the second unique sublaminate, wherein the first unique sublaminate and the second unique sublaminate are distinct from one another. Various other apparatuses, systems, and methods are also disclosed.
ELECTRONIC DEVICE
An electronic device according to an embodiment includes first and second substrates, first and second conductors, and an electronic component. The first substrate includes a first connector portion, first pad portions, and a first transmission line. The first pad portions include a second pad portion, the first transmission line coupling the second pad portion and the first connector portion. The second substrate includes third pad portions. The third pad portions include a fourth pad portion and a fifth pad portion. The first conductor is coupled to the fourth pad portion and to the second pad portion. The second conductor is coupled to the fifth pad portion. The first electronic component has one end coupled to the first conductor and other end coupled to the second conductor.
Multilayer printed circuit board and method for manufacturing the same
A multilayer printed circuit board providing large current and high power includes an inner circuit laminated structure, a first adding-layer circuit base board, and second adding-layer circuit base board. The inner circuit laminated structure includes at least one first type and second type conductive circuit layer alternately stacked. The first and second type conductive circuit layer are respectively made of first and second type metal layer, the first and second type metal layer have different etching ability. The second adding-layer circuit base board and the first adding-layer circuit base board are formed on opposite surfaces of the inner circuit laminated structure. The first and second adding-layer circuit base boards are electrically connected to the inner circuit laminated structure. The disclosure also provides a method for manufacturing such multilayer printed circuit board.
Circuit board
The disclosure provides a circuit board that includes: a carrier element having a number of circuit board layers; a number of electronic components; a number of thermal interfaces; and a number of electrical interfaces. The electronic components are arranged directly on at least one of the surface sides on the carrier element. The opposite surface side of the carrier element is of potential-free design. Additionally, the circuit board with the electronic components is overlaid by a covering material in such a way that the electronic components are mechanically stabilized and the thermal and/or electrical interfaces are free of the covering material.
Printed circuit boards with plated blind slots for improved vertical electrical and/or thermal connections
In one aspect, a PCB is provided. The PCB includes at least one insulating layer, a blind slot, and at least one via. The at least on insulating layer includes a first surface and a second surface opposite the first surface. The blind slot is plated and formed in the at least one insulating layer, where the blind slot partially extends from the first surface to the second surface, and where the blind slot includes a conductive plating bonded along a major surface of the blind slot. The at least one via is electrically conductive and filled, where the at least one via is coupled with and extends between the conductive plating of the blind slot and the second surface of the at least one insulating layer.
MICRO-GROUND VIAS FOR IMPROVED SIGNAL INTEGRITY FOR HIGH-SPEED SERIAL LINKS
An information handling system includes a printed circuit board, a surface mount connector including first and second surface mount connector portions, first and second different pairs, and a ground plane. The first and second surface mount connector portions are mounted on the printed circuit board. The first differential pair is located on the first surface mount connector portion, and the second differential pair is located on the second surface mount connector portion. The ground plane is located in between the first and second surface mount connector portions within the printed circuit board. The first ground via is in physical communication with the ground plane and a first ground pad on a surface of the printed circuit board. The second ground via is in physical communication with the ground plane and a second ground pad on the surface of the printed circuit board.
Display device
Provided is a display device including: a display panel in which a display area and a non-display area located around the display area are defined; an external device which is disposed on the non-display area of the display panel; and a cover member which is disposed on the external device, wherein the external device includes a driving chip and a printed circuit film which is disposed on the non-display area of the display panel and spaced apart from the display area with the driving chip interposed between the printed circuit film and the display area in plan view, and the cover member includes a first insulating tape disposed on the external device, a first conductive tape disposed on the first insulating tape and a second insulating tape disposed on the first conductive tape, wherein the second insulating tape includes an electrostatic induction opening penetrating the second insulating tape in a thickness direction, a planar size of the first conductive tape is greater than a planar size of the second insulating tape, the first conductive tape protrudes further toward the display area than the second insulating tape in plan view, and the electrostatic induction opening is disposed on a part of the first conductive tape which protrudes further toward the display area than the second insulating tape.