A printed circuit board may include a substrate body portion, conductive patterns on a top surface of the substrate body portion, and a photosensitive insulating layer on the top surface of the substrate body portion and including an opening exposing at least one of the conductive patterns. The photosensitive insulating layer includes first to third sub-layers stacked sequentially. The first sub-layer includes an amine compound or an amide compound A refractive index of the second sub-layer is lower than a refractive index of the third sub-layer. A photosensitizer content of the second sub-layer is higher than a photosensitizer content of the third sub-layer.

A printed circuit board includes a first insulating layer having a through hole, and a via disposed to fill the through hole and to be extended to at least one surface of the first insulating layer, wherein the via includes a plating layer having an inner wall part disposed on an inner wall of the through hole and a land part extended from the inner wall part and disposed on the at least one surface of the first insulating layer, and a metal paste layer including metal particles, and filled in the rest of the through hole and disposed on the plating layer.

A multi-layer metal core printed circuit board (MCPCB) has mounted on it at least one or more heat-generating LEDs and one or more devices configured to provide current to the one or more LEDs. The one or more devices may include a device that carries a steep slope voltage waveform. Since there is typically a very thin dielectric between the patterned copper layer and the metal substrate, the steep slope voltage waveform may produce a current in the metal substrate due to AC coupling via parasitic capacitance. This AC-coupled current may produce electromagnetic interference (EMI). To reduce the EMI, a local shielding area may be formed between the metal substrate and the device carrying the steep slope voltage waveform. The local shielding area may be conductive and may be electrically connected, to a DC voltage node adjacent to the one or more devices.

A printed circuit board (PCB) having an engineered thermal path and a method of manufacturing are disclosed herein. In one aspect, the PCB includes complementary cavities formed on opposite sides of the PCB. The complementary cavities are in a thermal communication and/or an electrical communication to form the engineered thermal path and each cavity is filled with a thermally conductive material to provide a thermal pathway for circuits and components of the PCB. The method of manufacturing may further include drilling and/or milling each cavity, panel plating the cavities and filling the cavities with a suitable filling material.

A manufacturing method of a circuit board includes: providing a first double-sided copper laminate including a dielectric layer, a first copper foil layer and a copper plating layer wherein the dielectric layer, wherein the dielectric layer defines a groove, the copper plating layer includes a first copper plating portion in the groove and a second copper plating portion beside the first copper plating portion. A double-sided circuit substrate including base layer and two first wiring layers is provided, wherein each first wiring layer includes a signal line. Conductive paste blocks are disposed in the base layer and on both sides of the signal line; and a first double-sided copper laminate is stacked on each side of the double-sided circuit substrate, disposing the signal line in the groove. The conductive paste blocks are pressed electrically connect same to the second copper plating portions. The present disclosure further provides a circuit board.

A component-embedded substrate includes: a plurality of insulating layers each including a wiring pattern formed on one surface; an embedded component including a connection terminal; and a plurality of vias that electrically connect the connection terminal to the wiring patterns adjacent to each other in a lamination direction. The plurality of insulating layers is laminated on the connection terminal. Each of the plurality of vias is composed of a via hole formed in the respective insulating layer of the plurality of the insulating layers and a conductive material provided in the via hole. One of the plurality of vias is a connection via directly connected to the connection terminal. Another of the plurality of vias is a first adjacent via adjacent to the connection via in the lamination direction. The first adjacent via is connected to the wiring pattern formed on a surface of a top insulating layer.

A component carrier with a stack including an electrically insulating layer structure and an electrically insulating structure has a tapering blind hole formed in the stack and an electrically conductive plating layer extending along at least part of a horizontal surface of the stack outside of the blind hole and along at least part of a surface of the blind hole. A minimum thickness of the plating layer at a bottom of the blind hole is at least 8 μm. A demarcation surface of the plating layer in the blind hole and facing away from the stack extends laterally outwardly from the bottom of the blind hole towards a lateral indentation and extends laterally inwardly from the indentation up to an outer end of the blind hole. An electrically conductive structure fills at least part of a volume between the plating layer and an exterior of the blind hole.

A printed circuit board includes: a first insulating layer; a first metal layer disposed on one surface of the first insulating layer; a second metal layer disposed on the other surface facing the one surface of the first insulating layer; a via penetrating through the first insulating layer to connect the first and second metal layers to each other; and a heterogeneous metal region disposed in at least one of an area in which the via is adjacent to the first insulating layer and an area in which the via is adjacent to the first metal layer, and including a material different from that of the via, wherein the heterogeneous metal region includes at least one of nickel (Ni), silicon (Si), and titanium (Ti).

A component carrier with an electrically insulating layer structure has opposed main surfaces, a through-hole, and an electrically conductive bridge structure connecting opposing sidewalls delimiting the through-hole. The sidewalls have a first tapering portion extending from a first main surface and a second tapering portion extending from a second main surface. A first demarcation surface faces the first main surface and a second demarcation surface faces the second main surface. A central bridge plane extends parallel to the first main surface and the second main surface and is at a vertical center between a lowermost point of the first demarcation surface and an uppermost point of the second demarcation surface. A first intersection point is between the central bridge plane and one of the sidewalls delimiting the through hole. A length of a shortest distance from the first intersection point to the first demarcation surface is at least 8 μm.

A printed circuit board according to an embodiment includes: an insulating layer including a via hole; and a via disposed in the via hole of the insulating layer, wherein the via includes; a connection portion disposed in the via hole of the insulating layer; a first pad disposed on an upper surface of the insulating layer and an upper surface of the connection portion; and a second pad disposed under a lower surface of the insulating layer and a lower surface of the connection portion, wherein the upper surface of the connection portion has a concave shape in a downward direction, the lower surface of the connection portion has a concave shape in an upward direction, a lower surface of the first pad has a convex shape corresponding to the upper surface of the connection portion, and an upper surface of the second pad has a convex shape corresponding to the lower surface of the connection portion.