A power semiconductor module includes a substrate with a metallization layer that is structured. A semiconductor chip having a first side bonded to the metallization layer. A metal clip, which is a strip of metal, has a first planar part bonded to a second side of the semiconductor chip opposite to the first side. The metal clip also has a second planar part bonded to the metallization layer. A mold encapsulation at least partially encloses the substrate and the metal clip. The mold encapsulation has a recess approaching towards the first planar part of the metal clip. The semiconductor chip is completely enclosed by the mold encapsulation, the substrate and the metal clip and the first planar part of the metal clip is at least partially exposed by the recess. A sensor is accommodated in the recess.

Damage to a joint part of a terminal of an electronic component mounted on a substrate is detected. The substrate includes a base material unit, a land, and a light detection unit. The land included in the substrate is arranged with a stress light emitting body configured to emit light in accordance with stress, includes a transparent member, and is joined with a terminal of an element arranged in the base material unit included in the substrate. The light detection unit included in the substrate is arranged between the base material unit and the land included in the substrate, and detects light from the stress light emitting body.

Embodiments presented in this disclosure generally relate to techniques for interconnecting integrated circuits. More specifically, embodiments disclosed herein provide a back mounted interposer (BMI) to facilitate interconnecting of integrated circuits. One example apparatus includes an integrated circuit, an interposer, and a circuit board, at least a portion of the circuit board being disposed between the integrated circuit and the interposer, where the circuit board is configured to provide electrical connection between the interposer and the integrated circuit via connection elements on a first surface of the interposer. The apparatus also includes an interface on a second surface of the interposer, the interface being configured to provide signals from the integrated circuit to an electrical component.

Disclosed herein are unitary printed circuit boards (PCBs) and methods of using them for testing an integrated circuit (IC). In some embodiments, a unitary PCB comprises a main board portion and a flexible PCB portion, which are configured to be detached from each other at a separation location on the unitary PCB. The main board portion comprises a plurality of pads, and the flexible PCB portion comprises a plurality of through-holes, where a layout of the through-holes corresponds to a layout of the plurality of pads. In some embodiments, a method of testing an IC of a device comprises separating the unitary PBC into a main board portion and a flexible PCB portion, attaching the IC to the main board portion, soldering the main board portion to a platform PCB of the device, and attaching the flexible PCB portion to the main board portion.

A printed circuit board (PCB) system includes a first printed circuit board (PCB), an integrated circuit (IC) package, and a memory module. The IC package includes i) a package substrate, ii) a main IC chip that is electrically coupled to a top surface of the package substrate, iii) first contact structures that are disposed on a bottom surface of the package substrate and that are electrically coupled to the first PCB, and iv) second contact structures that are disposed on a top surface of the package substrate. The memory module includes i) a second PCB, ii) one or more memory IC chips that are disposed on the second PCB, and iii) third contact structures that are disposed on a bottom surface of the second PCB. An interposer electrically couples the second contact structures of the IC package with the third contact structures of the memory module.

A method of making an electronic device may include forming at least one circuit layer that includes solder pads on a substrate and forming at least one liquid crystal polymer (LCP) solder mask having mask openings therein. The method may also include forming at least one thin film resistor on the LCP solder mask and coupling the at least one LCP solder mask to the substrate so that the at least one thin film resistor is coupled to the at least one circuit layer and so that the solder pads are aligned with the mask openings.

Provided is a matable electrical connection structure including a female connection member and a male connection member respectively including a plurality of first connection portions and a plurality of second connection portions, and a plurality of matable connection portions configured to detachably couple the female connection member and the male connection member, and respectively and electrically connect the plurality of first connection portions to the plurality of second connection portions, and the matable connection portions include inner conductive materials respectively and electrically connected to the plurality of first connection portions and provided on inner walls of a plurality of insertion holes formed in the female connection member, columns respectively and electrically connected to the plurality of second connection portions and configured to protrude from the male connection member to be inserted into the insertion hole, and elastic fins configured to extend outside the column to elastically contact the inner conductive material, and at least one of the female connection member and the male connection member is divided into a plurality of areas, and the plurality of matable connection portions are disposed to form a group in each of the areas.

A semiconductor device, a circuit board structure and a manufacturing forming thereof are provided. A circuit board structure includes a core layer, a first build-up layer and a second build-up layer. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The circuit board structure has a plurality of stress releasing trenches extending into the first build-up layer and the second build-up layer.

An electronic device and methods for fabricating the same are disclosed herein that utilize a dam formed on a printed circuit board (PCB) that is positioned to substantially prevent edge bond material, utilized to secure a chip package to the PCB, from interfacing with the solder balls transmitting signals between the PCB and chip package.

Systems, methods, and devices for a ball grid array with non-linear conductive routing are described herein. Such a ball grid array may include a plurality of solder balls that are electrically coupled by a non-linear conductive routing. The non-linear conductive routing may include a plurality of routing sections where each of the plurality of routing sections is disposed at an angle to adjacent routing sections.