The concepts, systems, circuits and techniques described herein are directed toward a spiral antenna which may be provided using additive manufacturing technology so as to provide an antenna capable of operation at frequencies which are higher than spiral antennas manufactured using standard photo-etch or printed circuit board (PCB) manufacturing processes.

A component carrier with a stack including an electrically insulating layer structure and an electrically insulating structure has a tapering blind hole formed in the stack and an electrically conductive plating layer extending along at least part of a horizontal surface of the stack outside of the blind hole and along at least part of a surface of the blind hole. A minimum thickness of the plating layer at a bottom of the blind hole is at least 8 μm. A demarcation surface of the plating layer in the blind hole and facing away from the stack extends laterally outwardly from the bottom of the blind hole towards a lateral indentation and extends laterally inwardly from the indentation up to an outer end of the blind hole. An electrically conductive structure fills at least part of a volume between the plating layer and an exterior of the blind hole.

A component carrier with an asymmetric build-up, which includes (a) a core; (b) a first stack at a first main surface of the core, the first stack having at least one first electrically conductive layer structure and a plurality of first electrically insulating layer structures; and (c) a second stack at a second main surface of the core, the second stack having at least one second electrically conductive layer structure and a plurality of second electrically insulating layer structures. At least two of the second electrically insulating layer structures are in direct contact with each other and each one of these electrically insulating layer structures has a smaller thickness than and/or includes a different material property than one of the first electrically insulating layer structures. Further described are methods for designing and manufacturing such an asymmetric component carrier.

Forming, in a printed-wiring board, a via sufficiently filled without residual smear, for use in an insulating layer and the size of the via to be formed. A via of a printed-wiring board comprises a first filling portion which fills at least a center portion of a hole, and a second filling portion which fills a region of the hole that is not filled with the first filling portion. An interface which exists between the second and first filling portions, or an interface which exists between the second filling portion and an insulating layer and the first filling portion has the shape of a truncated cone comprising a tapered surface which is inclined to become thinner from a first surface toward a second surface, and an upper base surface which is positioned in parallel to the second surface and closer to the first surface than to the second surface.

A wiring circuit board includes a porous insulating layer, and a first conductive layer sequentially toward one side in the thickness direction. The first conductive layer includes a first signal wire and first ground wires. Each of the first ground wires is thicker than the first signal wire.

The main technical problem solved by the present disclosure is to provide a circuit board preparation method. The method includes: obtaining a to-be-processed plate comprising an insulating layer, a first copper layer, a second copper layer opposite to the first copper layer, a blind metalized hole, and a first tab facing the blind metalized hole; obtaining a white insulating material; laminating the white insulating material to a surface of the insulating layer, a surface of the first copper layer, a surface of the first tab, and a surface of the second copper layer to form a first white insulating medium layer and a second white insulating medium layer opposite to the first while insulating medium layer; and performing surface polishing for the first white insulating medium layer and grinding the first white insulating medium layer until the first tab is exposed to form a first white reflective layer.

A substrate is manufactured by drilling a chip containing groove in a composite inner layer circuit structure, having a component connecting end of a circuit layer protruding from a mounting side wall in the chip containing groove, mounting a chip component in the chip containing groove, and connecting the surface bonding pad to the component connecting end. The chip component in the present invention penetrates at least two circuit layers, and the surface bonding pad is bonded to the component connecting end of the circuit layer directly, reducing the occupied area of the chip component in each one of the circuit layers, and increasing the area for circuit disposing and the possible amount of chip components that may be mounted in the substrate.

A printed circuit board according to an embodiment includes an insulating layer; and a via portion disposed on the insulating layer; wherein the via portion includes: a first pad disposed under the insulating layer; a second pad disposed on the insulating layer; and a via part disposed between the first and second pads in the insulating layer; and wherein a width of the first pad is less than or equal to a width of a lower surface of the via part.

An electronics module (100), especially a power electronics module, comprising a metal-ceramic substrate (1) serving as a carrier and having a ceramic element (10) and a primary component metallization (21), an insulation layer (40) directly or indirectly connected to the primary component metallization (21), and a secondary component metallization (22) which is connected to the side of the insulation layer (40) facing away from the metal-ceramic substrate (1) and is especially isolated from the primary component metallization (21) using the insulation layer (40), wherein the ceramic element (10) has a first size (L1, D1) and the insulation layer (40) has a second size (L2, D2) and a ratio of the second size (L2, D2) to the first size (L1, D1) has a value smaller than 0.8, to form an island-like insulation layer (40) on the primary component metallization (21).

A multilayer circuit board includes an upper surface and an opposing lower surface. An electrically insulating layer is disposed between the upper and lower surfaces. A plurality of electrically conductive upper and lower rear pads are disposed proximate a rear edge on the respective upper and lower surfaces for termination of a plurality of wires. The upper and lower rear pads include respective upper and lower rear ground pads substantially aligned with each other and configured for termination of ground wires. A plurality of electrically conductive front pads are disposed proximate a front edge for insertion into a connector and electrically connected to the upper and lower rear pads. An electrically conductive via extends from the upper rear ground pad to the lower rear ground pad and makes electrical and physical contact with each of the upper and lower rear ground pads.