Provided is a cross-linkable arylamine-based compound represented by Formula 1a or 1b, a polymer obtained therefrom, a light-emitting device including the polymer, and an electronic apparatus including the light-emitting device. The light-emitting device includes a first electrode; a second electrode facing the first electrode; and an intermediate layer between the first electrode and the second electrode and comprising an emission layer, wherein the intermediate layer includes at least one of the arylamine-based polymer formed by cross-linking a cross-linkable arylamine-based compound represented by Formula 1a or 1b.

The present invention provides a self-healing field-effect transistor (FET) device comprising a self-healing substrate and a self-healing dielectric layer, said substrate and said layer comprising a disulfide-containing poly(urea-urethane) (PUU) polymer, wherein the dielectric layer has a thickness of less than about 10 μm, a gate electrode, at least one source electrode, and at least one drain electrode, said electrodes comprising electrically conductive elongated nanostructures; and at least one channel comprising semi-conducting elongated nanostructures. Further provided is a method for fabricating the FET device.

The present application relates to an organic electronic device, said electronic device comprising a multi-layer electrode as well as an organic semiconducting layer, as well as to a method for producing such organic electronic device.

A compound of Formula 1, as disclosed herein, is useful in an organic light emitting device and apparatuses including the same.

A technique, comprising: forming in situ on a support substrate: a first metal layer; a light-absorbing layer after the first metal layer; a conductor pattern after the light-absorbing layer; and a semiconductor layer after the conductor pattern; patterning the semiconductor layer using a resist mask to form a semiconductor pattern defining one or more semiconductor channels of one or more semiconductor devices; and patterning the light-absorbing layer using the resist mask and the conductor pattern, so as to selectively retain the light-absorbing layer in regions that are occupied by at least one of the resist mask and the conductor pattern.

A memory device according to an embodiment includes a fluid layer extending in a first direction, a particle in the fluid layer, a first control electrode made of a first material, a first insulating film provided between the fluid layer and the first control electrode, a second control electrode made of a second material and provided to be spaced apart from the first control electrode in the first direction, a second insulating film provided between the fluid layer and the second control electrode, a third control electrode made of a third material different from the first material and the second material and provided between the first control electrode and the second control electrode, and a third insulating film provided between the fluid layer and the third control electrode.

An organic thin film transistor includes a gate electrode, an organic semiconductor layer overlapped with the gate electrode, a hydrophilic nanolayer on the organic semiconductor layer, and a source electrode and a drain electrode electrically connected to the organic semiconductor layer.

A self-healing field-effect transistor (FET) device is disclosed in this application, the self-healing FET has a self-healing substrate, a self-healing dielectric layer, a gate electrode, at least one source electrode, at least one drain electrode, and at least one channel. The self-healing substrate and the self-healing dielectric layer have a disulfide-containing poly(urea-urethane) (PUU) polymer. The self-healing dielectric layer has a thickness of less than about 10 .Math.m. The electrodes have electrically conductive elongated nanostructures. The at least one channel has semi-conducting elongated nanostructures.

A back-gate carbon nanotube field effect transistor (CNFETs) provides: (1) reduced parasitic capacitance, which decreases the energy-delay product (EDP) thus improving the energy efficiency of digital systems (e.g., very-large-scale integrated circuits) and (2) scaling of transistors to smaller technology nodes (e.g., sub-3 nm nodes). An exemplary back-gate CNFET includes a channel. A source and a drain are disposed on a first side of the channel. A gate is disposed on a second side of the channel opposite to the first side. In this manner, the contacted gate pitch (CGP) of the back-gate CNFET may be scaled down without scaling the physical gate length (L.sub.G) or contact length (L.sub.C). The gate may also overlap with the source and/or the drain in this architecture. In one example, an exemplary CNFET was demonstrated to have a CGP less than 30 nm and 1.6× improvement to EDP compared to top-gate CNFETs.

In a method of forming a gate-all-around field effect transistor, a gate structure is formed surrounding a channel portion of a carbon nanotube. An inner spacer is formed surrounding a source/drain extension portion of the carbon nanotube, which extends outward from the channel portion of the carbon nanotube. The inner spacer includes two dielectric layers that form interface dipole. The interface dipole introduces doping to the source/drain extension portion of the carbon nanotube.