H10K10/486

DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME

The invention provides a display apparatus and a method for manufacturing the same. The display apparatus includes a substrate and a thin-film transistor. The thin-film transistor includes a semiconductor layer disposed on the substrate and includes a gate electrode overlapping the semiconductor layer and insulated from the semiconductor layer. The semiconductor layer includes a polysilicon layer and an organic layer. The polysilicon layer has a first surface and has an uneven surface overlapping the first surface. The organic layer is disposed on the uneven surface of polysilicon layer and includes an organic semiconductor material.

THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME, DISPLAY DEVICE
20220320449 · 2022-10-06 ·

A thin film transistor, a method for manufacturing the same and a display device are disclosed, the thin film transistor includes: a first electrode, a second electrode, an active layer and a flexible conductive layer located on a substrate, one of the first electrode and the second electrode is a source, and the other thereof is a drain; the active layer is electrically coupled with the first electrode, and an orthographic projection of the active layer on the substrate is within an orthographic projection of the first electrode on the substrate; the flexible conductive layer is located on a side of the active layer away from the first electrode, and electrically couples the active layer with the second electrode.

Methods of manufacturing a field effect transistor using carbon nanotubes and field effect transistors

In a method of forming a gate-all-around field effect transistor, a gate structure is formed surrounding a channel portion of a carbon nanotube. An inner spacer is formed surrounding a source/drain extension portion of the carbon nanotube, which extends outward from the channel portion of the carbon nanotube. The inner spacer includes two dielectric layers that form interface dipole. The interface dipole introduces doping to the source/drain extension portion of the carbon nanotube.

Single electron transistor (SET), circuit containing set and energy harvesting device, and fabrication method
11649525 · 2023-05-16 ·

A method for fabricating a single electron transistor is provided. A substrate includes a substantially planar surface with a source electrode, a drain electrode, and a gate electrode thereon, with the source and drain electrodes spaced apart from one another by a gap. The source electrode and the drain electrode are electrified, and a single nanometer-scale conductive particle is electrospray deposited in the gap. The single nanometer-scale conductive particle has an effective size of not greater than 10 nanometers. At least one carbon nanotube is deposited on the substrate and subjected to dielectrophoresis to position the carbon nanotube within 1 nanometer of the single nanometer-scale conductive particle. The at least one carbon nanotube establishes a first connection between the source electrode and the single nanometer-scale conductive particle and a second connection between the drain electrode and the single nanometer-scale conductive particle.

OFETS HAVING MULTILAYER ORGANIC SEMICONDUCTOR WITH HIGH ON/OFF RATIO

An organic field effect transistor includes a channel structure having a photoalignment layer and an organic semiconductor layer disposed directly over the photoalignment layer, where a charge carrier mobility varies along a thickness direction of the channel structure. The channel structure may define an active area between a source and a drain of the transistor and may include alternating layers of at least two photoalignment layers and at least two organic semiconductor layers. Each photoalignment layer is configured to influence an orientation of molecules within an overlying organic semiconductor layer and hence impact the mobility of charge carriers within the device active area while also advantageously decreasing the OFF current of the device.

HETEROAROMATIC COMPOUNDS FOR ORGANIC ELECTRONICS

The present invention provides compounds of formula (I) wherein X is O, S or NR.sup.10, wherein R.sup.10 is H, C.sub.1-30-alkyl, substituted C.sub.1-30-alkyl, C.sub.2-30-alkenyl, substituted C.sub.2-30-alkenyl, C.sub.2-30-alkynyl, substituted C.sub.2-30-alkynyl or C(0)-OR, R.sup.1 and R.sup.11 are independently from each other selected from the group consisting of C.sub.1-30-alkyl, substituted C.sub.1-30-alkyl, C.sub.2-30-alkenyl, substituted C.sub.2-30-alkenyl, C.sub.2-30-alkynyl, substituted C.sub.2-30-alkynyl, C.sub.5-8-cycloalkyl, substituted C.sub.5-8-cycloalkyl, C.sub.5-8-cycloalkenyl, and substituted C.sub.5-8-cycloalkenyl, and an electronic device comprising the compounds as semiconducting material.

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Method of p-type doping carbon nanotube

A method of p-type doping a carbon nanotube includes the following steps: providing a single carbon nanotube; providing a layered structure, wherein the layered structure is a tungsten diselenide film or a black phosphorus film; and p-type doping at least one portion of the carbon nanotube by covering the carbon nanotube with the layered structure.

Method of making N-type thin film transistor

A method of making N-type semiconductor layer includes following steps. An insulating substrate is provided. An MgO layer is deposited on the insulating substrate. A first dielectric layer is formed by acidizing the MgO layer. A semiconductor carbon nanotube layer is formed to cover the MgO layer. A source electrode and drain electrode are formed to be electrically connected to the semiconductor carbon nanotube layer. A second dielectric layer is applied on the semiconductor carbon nanotube layer. A gate electrode is formed on the second dielectric layer.

SEMICONDUCTOR DEVICE
20230187559 · 2023-06-15 · ·

A semiconductor device, including a first gate, a second gate, a third gate, a first semiconductor layer, a second semiconductor layer, a source, and a drain, is provided. The first semiconductor layer is located between the first gate and the second gate. The second gate is located between the first semiconductor layer and the second semiconductor layer. The second semiconductor layer is located between the second gate and the third gate. The source is electrically connected to the first semiconductor layer and the second semiconductor layer. The drain is electrically connected to the first semiconductor layer and the second semiconductor layer.

Four-terminal gate-controlled thin-film organic thyristor

Technologies are generally described for a four-terminal, gate-controlled, thin-film thyristor device. The thyristor device may essentially be an n-type thin-film transistor (TFT) with an additional emitter terminal. The thyristor device may exhibit an S-shaped negative differential resistance (NDR) characteristic resulting from conductance modulation. The conductance modulation may be caused by formation of a secondary channel for current flow due to an inherent structure of the device. The secondary channel may be formed in a semiconductor area within the device, the semiconductor area including a hole transporting organic semiconductor layer (HTL) and an electron transporting organic semiconductor layer (ETL). A gate terminal of the thyristor device may further allow onset of NDR characteristics to be controlled and may allow the device to be switched off.