A GHeT includes a bottom gate formed on a substrate; a first dielectric layer (DL) formed on the bottom gate; a monolayer film formed of an atomically thin material on the first DL; a bottom contact (BC) formed on part of the monolayer film; a second DL formed on the BC; a top contact (TC) formed on the second DL on top of the BC; a network of CNTs formed on the TC and the monolayer film, to define an overlap region with the monolayer film; a third DL formed on the CNT network, the monolayer film and the TC; and a top gate formed on the third DL and overlapping with the overlap region. Such GHeT design allows gate tunability of Gaussian peak position, height and width that define Gaussian transfer characteristic, thereby enabling simplified circuit architectures for various spiking neuron functions for emerging neuromorphic applications.

A carbon nanotube composite structure includes a carbon nanotube and a film-like structure. The carbon nanotube includes a p-type portion and an n-type portion. The film-like structure is a molybdenum disulfide film or a tungsten disulfide film, and the film-like structure covers the n-type portion.

A method of p-type doping a carbon nanotube includes the following steps: providing a single carbon nanotube; providing a layered structure, wherein the layered structure is a tungsten diselenide film or a black phosphorus film; and p-type doping at least one portion of the carbon nanotube by covering the carbon nanotube with the layered structure.

A tunneling transistor includes a gate, an insulating layer placed on the gate, a carbon nanotube being semiconducting, a film-like structure, a source electrode, and a drain electrode. The carbon nanotube is placed on a surface of the insulating layer away from the gate. The film-like structure covers a portion of the carbon nanotube, and the film-like structure is a molybdenum disulfide film or a tungsten disulfide film. The source electrode is electrically connected to the film-like structure. The drain electrode is electrically connected to the carbon nanotube.

A method for enhancing the performance of pentacene organic field-effect transistor (OFET) using n-type semiconductor interlayer: an n-type semiconductor thin film was set between the insulating layer and the polymer electret in the OFET with the structure of gate-electrode/insulating layer/polymer/pentacene/source (drain) electrode. The thickness of n-type semiconductor layer is 1˜200 nm. The induced electrons at the interface of n-type semiconductor and polymer electret lead to the reduction of the height of the hole-barrier formed at the interface of polymer and pentacene, thus effectively reducing the programming/erasing (P/E) gate voltages of pentacene OFET, adjusting the height of hole barrier at the interface of polymer and pentacene to a reasonable scope by controlling the quantity of induced electrons in n-type semiconductor layer, thus improving the performance of pentacene OFET, such as the P/E speeds, P/E endurance and retention characteristics.

A method includes forming a first low-dimensional layer over an isolation layer, forming a first insulator over the first low-dimensional layer, forming a second low-dimensional layer over the first insulator, forming a second insulator over the second low-dimensional layer, and patterning the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator into a protruding fin. Remaining portions of the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator form a first low-dimensional strip, a first insulator strip, a second low-dimensional strip, and a second insulator strip, respectively. A transistor is then formed based on the protruding fin.

The present invention relates to a composition comprising an electron-transporting host and a hole-transporting host, to the use thereof in electronic devices and electronic devices comprising said composition. The electron-transporting host is more preferably selected from the class of the triazine-dibenzofuran-carbazole systems or the class of the triazine-dibenzothiophene-carbazole systems. The hole-transporting host is preferably selected from the class of biscarbazoles.

A self-aligned short-channel SASC electronic device includes a first semiconductor layer formed on a substrate; a first metal layer formed on a first portion of the first semiconductor layer; a first dielectric layer formed on the first metal layer and extended with a dielectric extension on a second portion of the first semiconductor layer that extends from the first portion of the first semiconductor layer, the dielectric extension defining a channel length of a channel in the first semiconductor layer; and a gate electrode formed on the substrate and capacitively coupled with the channel. The dielectric extension is conformally grown on the first semiconductor layer in a self-aligned manner. The channel length is less than about 800 nm, preferably, less than about 200 nm, more preferably, about 135 nm.

Provided are devices and methods to detect the presence of volatile organic compounds related to the presence of a disease state in a biological sample. The devices may include a detection moiety such as a polynucleoide in electronic communication with a semiconductor such as graphene or a carbon nanotube.

An organic field effect transistor includes a channel structure having a photoalignment layer and an organic semiconductor layer disposed directly over the photoalignment layer, where a charge carrier mobility varies along a thickness direction of the channel structure. The channel structure may define an active area between a source and a drain of the transistor and may include alternating layers of at least two photoalignment layers and at least two organic semiconductor layers. Each photoalignment layer is configured to influence an orientation of molecules within an overlying organic semiconductor layer and hence impact the mobility of charge carriers within the device active area while also advantageously decreasing the OFF current of the device.