Semiconductor power device with corresponding package and related manufacturing process

Abstract

A semiconductor power device has: a die, with a front surface and a rear surface, and with an arrangement of projecting regions on the front surface, which define between them windows arranged within which are contact regions; and a package, which houses the die inside it. A metal frame has a top surface and a bottom surface; the die is carried by the frame on the top surface; an encapsulation coating coats the frame and the die. A first insulation multilayer is arranged above the die and is formed by an upper metal layer, a lower metal layer, and an intermediate insulating layer; the lower metal layer is shaped according to an arrangement of the projecting regions and has contact projections, which extend so as to electrically contact the contact regions, and insulation regions, interposed between the contact projections, in positions corresponding to the projecting regions.

Claims

1. A semiconductor power device, comprising: a semiconductor die comprising a first surface and a second surface, wherein a plurality of contact pads and a plurality of source regions are located at a first surface, the plurality of source regions having a longitudinal length that extends parallel to the first surface of the semiconductor die, the second surface forming a drain region; a leadframe, the second surface of the semiconductor die coupled to a surface of the leadframe and forms a drain region; and a multilayer stack arranged above the semiconductor die and including an upper metal layer, a lower metal layer, and an intermediate insulating layer between the upper and lower metal layers, wherein the lower metal layer comprises a plurality of contact projections extending toward the semiconductor die and electrically coupled to the source regions of the semiconductor die, wherein insulation regions are between the plurality of contact projections and face respective gate regions of the plurality of gate regions.

2. The device according to claim 1, wherein the second surface is coupled to the surface of the leadframe by a conductive material.

3. The device according to claim 1, further comprising an encapsulation material around portions of the semiconductor die and the multilayer stack.

4. The device according to claim 1, wherein the upper metal layer defines an outer surface of the semiconductor power device.

5. The device according to claim 1, wherein a surface of the leadframe defines, at least in part, an outer surface of the semiconductor power device.

6. The device according to claim 1, wherein the semiconductor die comprises power MOSFET.

7. A process, comprising: coupling a semiconductor die to a leadframe, wherein a first surface of the semiconductor die comprises a plurality of source regions, a plurality of gate regions, and one or more contact pads coupled to the plurality of gate regions, wherein the semiconductor die comprises a drain at a second surface, wherein the plurality of source regions are rectangular shaped in plan view at the first surface; and coupling a first multilayer stack to the active surface of the semiconductor die, the first multilayer stack including an upper metal layer, a lower metal layer, and an insulating layer between the upper metal layer and the lower metal layer, wherein the lower metal layer comprises a plurality of contact projections extending toward the semiconductor die and electrically coupled to the plurality of source regions of the semiconductor die, wherein insulation regions are provided between the plurality of contact projections and coupled to the plurality of gate regions.

8. The process according to claim 7, wherein the plurality of contact pads include one or more metallization layers.

9. The process according to claim 8, wherein the insulation regions form trenches between the contact projections and are arranged to house passivation regions coating portions of the one or more metallization layers.

10. The process according to claim 7, wherein the semiconductor die is a MOSFET, and wherein coupling a semiconductor die to a leadframe comprises coupling a drain region of the MOSFET.

11. The process according to claim 7, further comprising forming an encapsulation material around the semiconductor die and the leadframe, wherein a surface of the leadframe remains exposed from the encapsulation material.

12. A semiconductor power device, comprising: a semiconductor package having a semiconductor die having an active surface having a plurality of source regions, a plurality of gate regions, and one or more contact pads coupled to the plurality of gate regions, wherein the semiconductor die comprises a drain at a second surface, wherein the plurality of source regions are rectangular shaped with a longitudinal length that extends in direction that is parallel with the first surface of the semiconductor die; and a multilayer stack arranged over the active surface, the multilayer stack including an upper metal layer, a lower metal layer, and an insulating layer between the upper and lower metal layers, wherein the lower metal layer comprises a plurality of contact projections that extend toward and are electrically coupled to the plurality of source regions of the semiconductor die, wherein insulation regions are provided at the plurality of contact projections and face respective gate regions of the plurality of gate regions.

13. The semiconductor power device according to claim 12, wherein the semiconductor package is a leadframe semiconductor package.

14. The semiconductor power device according to claim 12, wherein the surface of the semiconductor die is coupled to a leadframe.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

(1) For a better understanding of the present disclosure preferred embodiments thereof are now described, purely by way of non-limiting example, with reference to the attached drawings, wherein:

(2) FIG. 1 is a schematic cross-sectional view of a semiconductor power device with a corresponding package of the SMD type, according to a first embodiment of the present solution;

(3) FIGS. 2A and 2B are schematic top plan views of a front surface of a die of the device of FIG. 1, in possible variant embodiments;

(4) FIG. 3 is a schematic cross-sectional view of a portion of a source contact clip of the device of FIG. 1;

(5) FIG. 4 is a schematic cross-sectional view of the source contact clip, during a possible manufacturing process;

(6) FIGS. 5A-5C are schematic cross-sectional views of the source contact clip, during successive steps of a different manufacturing process;

(7) FIG. 6 is a schematic cross-sectional view of the source contact clip, in a further variant embodiment;

(8) FIG. 7 is a perspective view of the package of the device of FIG. 1, in a first variant embodiment;

(9) FIG. 8 is a perspective view of the package of the device of FIG. 1, in a second variant embodiment; and

(10) FIG. 9 is a schematic cross-sectional view of a semiconductor power device with a corresponding package of the SMD type, according to a second embodiment of the present solution.

DETAILED DESCRIPTION

(11) With reference to FIG. 1, a first embodiment of a package 1 for a semiconductor power device 2, in particular a power MOSFET device is now disclosed. As will be highlighted hereinafter, the package 1 is in this case of the double-exposed type with dual-side cooling, with electrical insulation limited to just a top side.

(12) The package 1 comprises a leadframe 3 provided with a frame 4, made up of a metal plate, for example of copper, having a top surface 4a and a bottom surface 4b. The bottom surface 4b of the frame 4 forms part of an exposed bottom surface 1b of the package 1, which can itself operate as heat sink or be coupled (in a way not illustrated herein) to an external heat sink so as to increase the heat dissipation capacity towards the outside.

(13) The package 1 further comprises an encapsulation material 5, made of insulating material, for example epoxy resin, which covers and coats the frame 4 at the top (leaving, as mentioned previously, the bottom surface 4b thereof exposed) and in general defines the interface towards the outside of the package 1.

(14) The semiconductor power device 2 comprises a die 6, having a front surface 6a and a rear surface 6b, the latter being coupled, via coupling with a first solder-paste layer 7a, to the top surface 4a of the frame 4 of the leadframe 3.

(15) The die 6 comprises a body of semiconductor material, for example silicon, integrated in which are, in a known way not illustrated in detail herein, a plurality of MOSFET elementary units (or cells), arranged in strips and having a vertical, columnar, structure, each provided with a respective gate region and a respective source region that are arranged at the front surface 6a. The semiconductor material body constitutes a drain region of the MOSFET, and a drain metallization 8, in direct electrical contact with the body, coats the rear surface 6b of the die 6, constituting a drain pad of the same MOSFET.

(16) The frame 4 of the leadframe 3 is in this case in electrical contact with the drain metallization 8 (hence not being electrically insulated); an external portion of the frame 4 protrudes from the encapsulation material 5 and defines at least one drain lead D of the semiconductor power device 2.

(17) As shown schematically in FIG. 2A (and in a way not illustrated in detail in the aforesaid FIG. 1), gate metallization lines 10 (the so-called “gate fingers”) are provided on the front surface 6a of the die 6, having a suitable distribution for enabling (in a known way, here not illustrated) biasing of all the gate regions of the MOSFET cells. The gate fingers 10, which may be continuous or, as in the example illustrated, have interruptions along their longitudinal extension, define between them (and on the front surface 6a of the die 6) top passivation areas 11, arranged within which are source contact regions 12 or windows (also referred to as “source pads”), in electrical contact with the source regions of the MOSFET cells (and isolated from the aforesaid gate fingers 10). In the example illustrated, the source contact regions 12 are arranged on the front surface 6a of the die 6 and are rectangular in plan view (in a horizontal plane in which the front surface 6a of the die 6 lies), moreover having mutually uniform dimensions.

(18) The aforesaid source contact regions 12 are arranged within the top passivation areas 11 generally at the same height as the gate fingers 10, which are, however, subsequently covered by passivation regions 10′ (in a way not illustrated in detail herein) and are hence raised with respect to the source contact regions 12 starting from the front surface 6a of the die 6.

(19) One or more gate pads 13 (see once again FIG. 1), carried by the front surface 6a of the die 6 are moreover electrically connected to the gate fingers 10 and enable electrical biasing thereof from the outside. One or more gate leads (not illustrated in FIG. 1) are electrically connected, for example by means of electrical wires 13′ within the encapsulation material 5, to corresponding gate pads 13.

(20) In the example shown in FIG. 2A, three gate fingers 10 are present, which define top passivation areas 11, arranged within which are respective source contact regions 12. However, it is evident that the distribution and number of gate fingers 10, top passivation areas 11, and source contact regions 12 may vary according to the characteristics and specifications of the semiconductor power device 2.

(21) For instance, FIG. 2B illustrates a further example, in which a single gate finger 10 is provided on the front surface 6a of the die 6, which defines two top passivation areas 11 and two respective source contact regions 12 provided inside the same top passivation areas 11.

(22) The package 1 of the semiconductor power device 2 further comprises (see again FIG. 1) a source clip 14, coupled, via a second solder-paste layer 7b, on the front surface 6a of the die 6 so as to be in electrical contact with the source contact regions 12, and moreover arranged so as to contact, laterally with respect to the die 6, one or more source leads S of the power device 2, which protrude, at least in part, from the encapsulation material 5.

(23) According to a particular aspect of the present solution, a main portion 14′ of the aforesaid source clip 14 is provided in a bottom layer of an insulation multilayer 16 (also referred to as a first multilayer stack), arranged above the die 6 to provide electrical insulation thereof with respect to an exposed top surface 1a of the package 1.

(24) In the embodiment illustrated in FIG. 1, the aforesaid insulation multilayer 16 is a DBC (Direct-Bonded Copper) multilayer constituted by an upper metal layer 16a and a lower metal layer 16b, both of copper, and by an intermediate insulating layer 16c made of a ceramic material, for example alumina (Al.sub.2O.sub.3), or alternatively aluminum nitride (AlN) or beryllium oxide (BeO), coupled together by means of high-temperature eutectic direct bonding; the intermediate insulating layer 16c electrically insulates the top and bottom metal layers 16a, 16b completely.

(25) The upper metal layer 16a of the insulation multilayer 16 (or, as in the example illustrated, an additional metal layer 17 coupled in contact onto the same upper metal layer 16a, for example via attaching or pressure bonding) forms part of the exposed top surface 1a of the package 1, which may operate itself as heat sink or be coupled (in a way not illustrated herein) to a further external heat sink so as to increase the heat dissipation capacity towards the outside.

(26) The bottom layer 16b of the insulation multilayer 16 defines the main portion 14′ of the source clip 14. The same source clip 14 further comprises a connecting portion 14″, which connects the aforesaid main portion 14′ to the one or more source leads S of the power device 2. This connecting portion 14″ may be formed integrally with the main portion 14′ or else be constituted by a distinct portion of metal material, which in the example is also made of copper, that extends laterally with respect to the die 6 and is coupled to the main portion 14′.

(27) According to a particular aspect of the present solution, the aforesaid main portion 14′ of the source clip 14 (or, likewise, the aforesaid lower metal layer 16b of the insulation multilayer 16) is suitably shaped so as to correspond to the conformation and arrangement of the gate fingers 10 (and to the corresponding passivation regions 10′) present on the front surface 6a of the die 6 or, in other words, is shaped specularly with respect to the source contact regions 12.

(28) In detail, and with reference first to FIG. 3, the lower metal layer 16b of the insulation multilayer 16 has a comb-like conformation, having: contact regions 18, which extend as projections towards the underlying die 6 so as to come into electrical contact, at corresponding bottom surfaces, with the source contact regions 12 (when the insulation multilayer 16 is coupled on the front surface 6a of the die 6); and insulation regions 19, interposed between the contact regions 18 and arranged in positions corresponding to the gate fingers 10 above and not contacting the passivation regions 10′ that coat the gate fingers 10, so as to bypass or pass over the same gate fingers 10, thus preventing damage to the passivation regions 10′.

(29) In particular, the aforesaid insulation regions 19 are constituted by trenches 19′, defined between the projections of the contact regions 18 and arranged so as to house, when the insulation multilayer 16 is coupled to the front surface 6a of the die 6, the passivation regions 10′ on the gate fingers 10, without contacting them in any point, due to the presence of a separation gap, denoted as a whole by g in FIG. 3, between the passivation regions 10′ on the gate fingers 10 and the side and bottom walls of the same trenches 19′.

(30) In the example of FIG. 3, three trenches 19′ are illustrated, having a non-uniform lateral extension. It is, however, evident that the number and conformation of the trenches 19′ may differ according to the arrangement and conformation of the gate fingers 10 on the front surface 6a of the die 6 and of the corresponding source contact regions 12.

(31) As illustrated schematically in FIG. 4, shaping of the lower metal layer 16b of the insulation multilayer 16 may be obtained by sawing the lower metal layer 16b for the formation the trenches 19′, after the same lower metal layer 16b has been coupled to the intermediate insulating layer 16c of the insulation multilayer 16.

(32) Alternatively, as illustrated schematically in FIG. 5A, deposition of adhesive strips 20 of an appropriate adhesive material may be envisaged on the intermediate insulating layer 16c of the insulation multilayer 16, prior to coupling of the lower metal layer 16b. In a way that is evident, these adhesive strips 20 are arranged and shaped in a way corresponding to the gate fingers 10 and have empty spaces 21 between them.

(33) These empty spaces 21 are to be filled by the lower metal layer 16b for definition of the contact regions 18, as illustrated in FIG. 5B, when the lower metal layer 16b is coupled to the intermediate insulating layer 16c of the insulation multilayer 16.

(34) Afterwards, as illustrated in FIG. 5C, the adhesive strips 20 are removed, via detachment and separation from the intermediate insulating layer 16c so as to form the trenches 19′ in the lower metal layer 16b.

(35) Alternatively, the adhesive strips 20 can be removed only in part, in the case where the trenches 19′, once the adhesive strips 20 have been partially removed, have a height such as to enable the presence of the separation gap g, preventing any contact between the passivation regions 10′ on the gate fingers 10 and the remaining strips—thus preventing any damage to the passivation regions 10′ during positioning of the source clip 14 on the front surface 6a of the die 6, arranging the bottom contact surfaces of the projections of the contact regions 18 to correspond to the source contact regions 12.

(36) In this case, as illustrated schematically in FIG. 6, definition of the adhesive strips 20 may be envisaged, with first portions 20′, designed to be removed and detached for definition of the trenches 19′, and with second portions 20″, made of a material different from that of the first portions, consisting of a permanent adhesive, which are to remain in contact with the intermediate insulating layer 16c after detachment of the first portions 20′. In this case, the aforesaid second portions 20″ define a respective bottom wall of the trenches 19′.

(37) The package 1 of the semiconductor power device 2 is represented schematically in FIG. 7, in this case in a version with protruding leads, among which in particular the source lead S and the drain lead D, as well as one or more gate leads G.

(38) In the same FIG. 7, the exposed portion of the additional metal layer 17 coupled at the top in contact with the upper metal layer 16a of the insulation multilayer 16 is also shown, which provides a heat-dissipation surface external to the package 1, electrically insulated from the terminals of the semiconductor power device 2.

(39) FIG. 8 shows, instead, an alternative version of the package 1 of the semiconductor power device 2, of the leadless type, which does not differ, as regards construction thereof, from what has been illustrated previously.

(40) The process for manufacturing the semiconductor power device 2 hence envisages the following consecutive steps:

(41) providing the leadframe 3, with definition of the corresponding frame 4 and of the source and gate leads S and G;

(42) depositing the first solder-paste layer 7a on the top surface 4a of the frame 4;

(43) positioning the die 6 (in which the cells of the MOSFET have previously been formed in a known way here not described in detail) and coupling it by soldering to the frame 4 of the leadframe 3;

(44) depositing the second solder-paste layer 7b on the front surface 6a of the die 6;

(45) positioning the insulation multilayer 16 on the front surface 6a of the die 6, with adhesion of the lower metal layer 16b (which has previously been machined and shaped in a way corresponding to the passivation regions 10′ coating the gate fingers 10, as discussed previously in detail) to the front surface 6a, by means of the aforesaid second solder-paste layer 7b that sets the bottom contact surfaces of the projections of the contact regions 18 in metallic (and hence electrical) contact with the source contact regions 12;

(46) positioning and coupling the source clip 14 (in particular, the corresponding connecting portion 14″) to the one or more source leads S of the semiconductor power device 2; and

(47) forming the encapsulation material 5 for definition of the package 1 of the semiconductor power device 2.

(48) With reference to FIG. 9, a second embodiment of the present solution is now described with reference to a package 1, once again of a double-exposed dual-side-cooling type, in this case with double electrical insulation, both on the exposed top surface 1a and on the exposed bottom surface 1b.

(49) In detail, the package 1 differs from what has been illustrated with reference to the first embodiment in that it comprises a further insulation multilayer (also referred to as a second multilayer stack), designated by 26, arranged in this case between the rear surface 6b of the die 6 and the top surface 4a of the frame 4 of the leadframe 3.

(50) Also in this case, the aforesaid further insulation multilayer 26 is a DBC (Direct-Bonded Copper) multilayer constituted by a respective upper metal layer 26a and a respective lower metal layer 26b, both made of copper, and a respective intermediate layer 26c made of ceramic material, for example alumina (Al.sub.2O.sub.3), or alternatively aluminum nitride (AlN) or beryllium oxide (BeO), coupled together by means of high-temperature eutectic direct bonding; the intermediate layer 26c also in this case electrically insulates the top and bottom metal layers 26a, 26b completely.

(51) In particular, the lower metal layer 26b is in this case coupled to the top surface 4a of the frame 4, by means of a third solder-paste layer 7c, whereas the upper metal layer 26a is coupled to the rear surface 6b of the die 6 by means of the first solder-paste layer 7a (hence being in contact with the drain metallization 8 of the semiconductor power device 2). Alternatively, and in a way not illustrated in the aforesaid FIG. 9, the further insulation multilayer 26 may constitute, with its lower metal layer 26b, the leadframe 3, exposed, directly and at the bottom, towards the outside, not covered by the encapsulation material 5 (there being in any case full correspondence and metallic continuity between the aforesaid lower metal layer 26b and the frame 4 of the leadframe 3).

(52) In this embodiment, the drain terminal is electrically insulated from the frame 4 of the leadframe 3, and a drain clip 28 is hence present, which electrically connects at least one drain lead D that protrudes in part from the encapsulation material 5, to an outer portion of the upper metal layer 26a of the further insulation multilayer 26 (not overlaid by the die 6).

(53) In this case, the manufacturing process hence envisages the following consecutive steps:

(54) providing the leadframe 3, with definition of the corresponding frame 4 and of the source, gate, and drain leads S, G, and D;

(55) depositing and attaching of the further insulation multilayer 26, by adhesion of the corresponding lower metal layer 26b to the top surface 4a of the frame 4, by means of the third solder-paste layer 7c (it should be noted that, in the variant in which the further insulation multilayer 26 defines, with the corresponding lower metal layer 26b, the frame 4 of the leadframe 3, use of this third solder-paste layer 7c is not envisaged);

(56) positioning and coupling the drain clip 28 to the one or more drain leads D of the semiconductor power device 2;

(57) depositing the first solder-paste layer 7a on the upper metal layer 26a of the further insulation multilayer 26;

(58) positioning the die 6 (in which the cells of the MOSFET have previously been formed) and coupling it by means of soldering to the upper metal layer 26a of the further insulation multilayer 26;

(59) depositing the second solder-paste layer 7b on the front surface 6a of the die 6;

(60) positioning the insulation multilayer 16 on the front surface 6a of the die 6, with adhesion of the lower metal layer 16b (which has previously been processed and shaped in a way corresponding to the passivation regions 10′ that overlie the gate fingers 10, as discussed previously) to the front surface 6a, by means of the aforesaid second solder-paste layer 7b, which sets the bottom contact surfaces of the projections of the contact regions 18 in metallic (and hence electrical) contact with the source contact regions 12;

(61) positioning and coupling the source clip 14 (in particular, the corresponding connecting portion 14″) to the one or more source leads S of the semiconductor power device 2; and

(62) forming the encapsulation material 5 for definition of the package 1 of the semiconductor power device 2, such as in a molding process.

(63) The advantages of the discussed solution emerge clearly from what has been described previously.

(64) In any case, it is pointed out that this solution allows to provide a semiconductor power device 2 having a package 1 having compact dimensions, for example with a maximum thickness in the vertical direction of just 2-3 mm.

(65) Moreover, the package 1 advantageously affords the possibility of cooling on both sides (with possibility of marked heat dissipation), and electrical insulation of just the top side, or of both the bottom and top sides of the package 1.

(66) Advantageously, due, in particular, to provision of the insulation multilayer 16, the distances of separation between the gate, source, and drain leads G, S, and D of the semiconductor power device 2 are high, for example around 5-7 mm, so as to obtain high insulation voltages, for example in the region of 1600 V for the package 1 with protruding leads or 2000 V for the package 1 without protruding leads.

(67) Moreover, the on-state resistance Rds.sub.on of the semiconductor power device 2 is particularly low.

(68) In general, the reliability and robustness of the semiconductor power device 2 are particularly high, without entailing high manufacturing costs.

(69) The aforesaid advantages make use of the semiconductor power device 2 particularly recommended in numerous fields of application, amongst which the automotive field, the field of solar energy and energy storage, and the field of electrical energy conversion.

(70) Finally, it is clear that modifications and variations may be made to what has been described and illustrated herein, without thereby departing from the scope of the present disclosure.

(71) For instance, it is highlighted that, even though the package solution has been described with particular reference to a MOSFET device, it can also find advantageous application for different semiconductor devices, in which passivation regions are present overlying metallization lines that protrude on the surface of the corresponding die, as well as interposed contact regions that have to be biased at different voltages.

(72) Further, the various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.