METHOD AND APPARATUS FOR READING DATA STORED IN FLASH MEMORY BY REFERRING TO BINARY DIGIT DISTRIBUTION CHARACTERISTICS OF BIT SEQUENCES READ FROM FLASH MEMORY
20210398596 · 2021-12-23
Assignee
Inventors
Cpc classification
G06F3/0659
PHYSICS
G11C16/0475
PHYSICS
G11C29/52
PHYSICS
G06F3/0679
PHYSICS
G11C2211/5648
PHYSICS
G11C16/0483
PHYSICS
G11C16/3427
PHYSICS
G06F3/0619
PHYSICS
International classification
G06F11/10
PHYSICS
G11C11/56
PHYSICS
G11C16/34
PHYSICS
G11C29/52
PHYSICS
Abstract
A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.
Claims
1. A memory controller for reading data stored in a flash memory, comprising: a control logic, for performing a plurality of read operations upon a plurality of memory cells of the flash memory, wherein the read operations utilizes a plurality of control gate voltages to read bits from memory cells; and a receiving circuit, for obtaining a plurality of bit sequences from the flash memory in response to the plurality of read operations; wherein the control logic refers to the plurality of bit sequences to determine numbers of memory cells whose threshold voltages are located between a first control gate voltage and a second control gate voltage of the plurality of control gate voltages, to generate a first value; and the control logic refers to the plurality of bit sequences to determine numbers of memory cells whose threshold voltages are located between a third control gate voltage and a fourth control gate voltage of the plurality of control gate voltages, to generate a second value; and the control logic updates at least one of the plurality of control gate voltages according to the first value and the second value.
2. The memory controller of claim 1, wherein the first control gate voltage is lower than the second control gate voltage, the second control gate voltage is lower than the third control gate voltage, and the third control gate voltage is lower than the fourth control gate voltage.
3. The memory controller of claim 2, wherein the first control gate voltage and the second control gate voltage are two adjacent control gate voltages, and the third control gate voltage and the fourth control gate voltage are two adjacent control gate voltages.
4. A method for reading data stored in a flash memory, comprising: performing a plurality of read operations upon a plurality of memory cells of the flash memory, wherein the read operations utilizes a plurality of control gate voltages to read bits from memory cells; obtaining a plurality of bit sequences from the flash memory in response to the plurality of read operations; referring to the plurality of bit sequences to determine numbers of memory cells whose threshold voltages are located between a first control gate voltage and a second control gate voltage of the plurality of control gate voltages, to generate a first value; referring to the plurality of bit sequences to determine numbers of memory cells whose threshold voltages are located between a third control gate voltage and a fourth control gate voltage of the plurality of control gate voltages, to generate a second value; and updating at least one of the plurality of control gate voltages according to the first value and the second value.
5. The method of claim 4, wherein the first control gate voltage is lower than the second control gate voltage, the second control gate voltage is lower than the third control gate voltage, and the third control gate voltage is lower than the fourth control gate voltage.
6. The method of claim 5, wherein the first control gate voltage and the second control gate voltage are two adjacent control gate voltages, and the third control gate voltage and the fourth control gate voltage are two adjacent control gate voltages.
7. An electronic device, comprising: a flash memory; and a flash memory controller, configured to control the flash memory; wherein the flash memory controller performs a plurality of read operations upon a plurality of memory cells of the flash memory, wherein the read operations utilizes a plurality of control gate voltages to read bits from memory cells, and the flash memory controller obtains a plurality of bit sequences from the flash memory in response to the plurality of read operations; wherein the flash memory controller refers to the plurality of bit sequences to determine numbers of memory cells whose threshold voltages are located between a first control gate voltage and a second control gate voltage of the plurality of control gate voltages, to generate a first value; and the flash memory controller refers to the plurality of bit sequences to determine numbers of memory cells whose threshold voltages are located between a third control gate voltage and a fourth control gate voltage of the plurality of control gate voltages, to generate a second value; and the flash memory controller updates at least one of the plurality of control gate voltages according to the first value and the second value.
8. The electronic device of claim 7, wherein the first control gate voltage is lower than the second control gate voltage, the second control gate voltage is lower than the third control gate voltage, and the third control gate voltage is lower than the fourth control gate voltage.
9. The electronic device of claim 8, wherein the first control gate voltage and the second control gate voltage are two adjacent control gate voltages, and the third control gate voltage and the fourth control gate voltage are two adjacent control gate voltages.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0012]
[0013]
[0014]
[0015]
[0016]
[0017]
[0018]
[0019]
[0020]
[0021]
[0022]
[0023]
[0024]
[0025]
[0026]
[0027]
[0028]
[0029]
[0030]
[0031]
[0032]
[0033]
[0034]
DETAILED DESCRIPTION
[0035] Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to . . . ”. Also, the term “couple” is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.
[0036] The generalized conception of the present invention is to read data stored in a flash memory by controlling the flash memory to perform a plurality of read operations upon each of a plurality of memory cells included in the flash memory (it should be noted that the read operations read bits of a predetermined bit order from each of the memory cells as one of the bit sequences by utilizing different control gate voltage settings), obtaining a plurality of bit sequences read from the memory cells, respectively, and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences. Further details are described as follows.
[0037] Please note that the threshold voltage distribution illustrated in the accompanying figures and values of the control gate voltages mentioned hereinafter are for illustrative purposes only, and are not meant to be limitations of the present invention. Besides, for simplicity and clarity, reading multiple bits stored by memory cells of one physical page in a NAND-type flash memory is taken as an example for illustrating technical features of the present invention. However, no matter whether the flash memory is a NAND-type flash memory or a flash memory of other type (e.g., a NOR-type flash memory), the spirit of the present invention is obeyed as long as binary digit distribution characteristics of bit sequences read from memory cells are used for determining readout information of the memory cells.
[0038] Please refer to
[0039] Please refer to
[0040] To identify LSBs of the memory cells M_0-M_K, the flash memory 102 sets the control gate voltage VG_0 by the threshold voltage VT_4 shown in
[0041] To identify CSBs of the memory cells M_0-M_K, the flash memory 102 sets the control gate voltage VG_0 by the threshold voltages VT_2 and VT_6 shown in
[0042] To identify MSBs of the memory cells M_0-M_K, the flash memory 102 sets the control gate voltage VG_0 by the threshold voltages VT_1, VT_3, VT_5, and VT_7 shown in
[0043] However, the threshold voltage distribution shown in
[0044] Please refer to
[0045] In this exemplary embodiment, the ECC circuit 110 may be implemented by a low density parity-check (LDPC) decoder. The control logic 106 controls the flash memory 102 to provide soft information to be decoded by the LDPC decoder. In other words, the aforementioned readout information generated from reading the memory cells M_0-M_K is soft information. Therefore, under the control of the control logic 106, the flash memory 102 outputs multiple binary digits to serve as one soft bit read from each of the memory cells M_0-M_K. Specifically, the control logic 106 is arranged for controlling the flash memory 102 to perform a plurality of read operations (e.g., seven read operations) upon each of the memory cells M_0-M_K of the target physical page P_0 when reading LSB data, CSB data, or MSB data. Please note that each read operation performed upon the memory cell may utilize a control gate voltage setting including one or more control gate voltages applied to a control gate of the memory cell; in addition, different read operations may utilize different control gate voltage settings. For example, a read operation for LSB data utilizes a gate voltage setting including one control gate voltage, a read operation for CSB data utilizes a gate voltage setting including two control gate voltages, and a read operation for MSB data utilizes a gate voltage setting including four control gate voltages. The receiving circuit 108 is coupled to the control logic 106, and arranged for obtaining a plurality of bit sequences BS_0, BS_1, . . . , BS_K read from the memory cells M_0-M_K, respectively, wherein the read operations read bits of a predetermined bit order (e.g., LSBs, CSBs, or MSBs) from each of the memory cells M_0-M_K as one of the bit sequences by utilizing different control gate voltage settings, and the bit sequences BS_0-BS_K may be buffered in the storage device 118 of the receiving circuit 108 for further processing.
[0046] Please refer to
[0047] In this exemplary embodiment, each bit sequence may have one of eight possible binary digit combinations BS1-BS8. When the electrical charge currently stored on the floating gate of the memory cell makes the threshold voltage of the memory cell higher than V.sub.LSB+3D, the bit sequence read from the memory cell would have the binary digit combination BS8=“0000000”. When the electrical charge currently stored on the floating gate of the memory cell makes the threshold voltage of the memory cell located between V.sub.LSB+2D and V.sub.LSB+3D, the bit sequence read from the memory cell would have the binary digit combination BS7=“0000010”. When the electrical charge currently stored on the floating gate of the memory cell makes the threshold voltage of the memory cell located between V.sub.LSB+D and V.sub.LSB+2D, the bit sequence read from the memory cell would have the binary digit combination BS6=“0001010”. When the electrical charge currently stored on the floating gate of the memory cell makes the threshold voltage of the memory cell located between V.sub.LSB and V.sub.LSB+D, the bit sequence read from the memory cell would have the binary digit combination BS5=“0101010”. When the electrical charge currently stored on the floating gate of the memory cell makes the threshold voltage of the memory cell lower than V.sub.LSB−3D, the bit sequence read from the memory cell would have the binary digit combination BS1=“1111111”. When the electrical charge currently stored on the floating gate of the memory cell makes the threshold voltage of the memory cell located between V.sub.LSB−2D and V.sub.LSB−3D, the bit sequence read from the memory cell would have the binary digit combination BS2=“1111110”. When the electrical charge currently stored on the floating gate of the memory cell makes the threshold voltage of the memory cell located between V.sub.LSB−D and V.sub.LSB−2D, the bit sequence read from the memory cell would have the binary digit combination BS3=“1111010”. When the electrical charge currently stored on the floating gate of the memory cell makes the threshold voltage of the memory cell located between V.sub.LSB and V.sub.LSB−D, the bit sequence read from the memory cell would have the binary digit combination BS4=“1101010”.
[0048] When all of the binary digits included in a bit sequence are 1's, this means that the corresponding memory cell has the electrical charge level L0, L1, L2, or L3, and the reliability of LSB=1 may be high. When all of the binary digits included in a bit sequence are 0's, this means that the corresponding memory cell has the electrical charge level L5, L6, L7, or L8, and the reliability of LSB=0 may be high. However, when a bit sequence has different binary digits “0” and “1” included therein, this means that the corresponding memory cell has the electrical charge level L3 or L4. As the threshold voltage of the corresponding memory cell is between V.sub.LSB−3D and V.sub.LSB+3D, the reliability of LSB=1/LSB=0 may be low due to the fact that the error probability may be high. For example, a memory cell which originally stores LSB=0 would have an amount of stored electrical charge corresponding to the electrical charge level L4 to make the threshold voltage higher than V.sub.LSB+3D. However, when the P/E count/retention time is increased, the amount of stored electrical charge is changed, which may make the threshold voltage lower than V.sub.LSB. Similarly, a memory cell which originally stores LSB=1 would have an amount of stored electrical charge corresponding to the electrical charge level L3 to make the threshold voltage lower than V.sub.LSB−3D. However, when the P/E count/retention time is increased, the amount of stored electrical charge is changed, which may make the threshold voltage higher than V.sub.LSB. To put it simply, when the threshold voltage distribution is changed, a memory cell which originally stores LSB=1 may be erroneously regarded as a memory cell which stores LSB=0, and a memory cell which originally stores LSB=0 may be erroneously regarded as a memory cell which stores LSB=1.
[0049] Therefore, the bit sequences each having one of the binary digit combinations BS2-BS7 should be monitored to track the threshold voltage distribution variation around the initial control gate voltage V.sub.LSB (i.e., the threshold voltage distribution variation between the electrical charge levels L3 and L4). The identifying unit 116 is therefore arranged for identifying a specific bit sequence of at least one specific memory cell, wherein each specific bit sequence has different binary digits “1” and “0” included therein. The determining unit 114 is coupled to the identifying unit, and arranged for determining an updated bit sequence of the at least one specific memory cell according to at least the specific bit sequence. By way of example, the determining unit 114 determines the updated bit sequence of the at least one specific memory cell by mapping the specific bit sequence to the updated bit sequence.
[0050] Please refer to
[0051] Next, the bit sequences BS_0-BS_K with one or more bit sequences updated/adjusted by the determining unit 114 according to the mapping rule are processed by the ECC circuit (e.g., an LDPC decoder) 110 again. As the number of error bits can be reduced by the determining unit 114 collaborating with the identifying unit 116, the ECC circuit 110 may have chance to successfully correct any error bits found in the currently processed readout information (i.e., soft information) of the physical page P_0. When the ECC corrector 122 indicates that the decoded result generated from the ECC circuit 110 is error-free, the read operation of reading LSB data of the memory cells M_0-M_K of the target physical page P_0 is accomplished. On the other hand, when the ECC corrector 122 indicates that the currently processed readout information still contains uncorrectable error bits, the determining unit 116 may further adjust the mapping rule for reducing the error probability of the specific bit sequence identified by the identifying unit 116.
[0052] In above exemplary embodiment, the determining unit 114 performs the mapping operation to update the specific bit sequences identified by the identifying unit 116. However, this is for illustrative purposes only, and is not meant to be a limitation of the present invention. In an alternative design, after the determining unit 144 determines that the shifted control gate voltage V.sub.LSB−D should be the optimum control gate voltage for identifying LSBs of memory cells M_0-M_K, the control unit 106 may be configured to set the initial control gate voltage by V.sub.LSB−D, and then control the flash memory 102 to perform seven read operations upon each of the memory cells M_0-M_K according to the updated initial control gate voltage V.sub.LSB−D and the voltage spacing D. Based on the same voltage adjusting order OD1, the flash memory 102 sets the control gate voltage VG_0 by V.sub.LSB−D, V.sub.LSB, V.sub.LSB−2D, V.sub.LSB+D, V.sub.LSB−3D, V.sub.LSB+2D, V.sub.LSB−4D, sequentially. Therefore, the flash memory 102 outputs new bit sequences BS_0-BS_M, wherein each of the new bit sequences BS_0-BS_M has seven binary digits sequentially obtained due to the control gate voltages V.sub.LSB−D, V.sub.LSB, V.sub.LSB−2D, V.sub.LSB+D, V.sub.LSB−3D, V.sub.LSB+2D and V.sub.LSB−4D. Next, the ECC circuit (e.g., an LDPC decoder) 110 processes the new bit sequences BS_0-BS_M (i.e., an updated codeword read from the physical page P_0) to correct any error bits found in the new bit sequences BS_0-BS_M. The same objective of generating readout information which can pass the ECC parity check is achieved.
[0053] Briefly summarized, in a case where each read operation utilizes only one control gate voltage applied to a control gate of each of the memory cells, and the control gate voltage utilized by one read operation is different from the control gate voltage utilized by another read operation, the identifying unit 116 is implemented for identifying any specific bit sequence having different binary digits included therein, and the determining unit 114 is implemented for determining updated specific bit sequence(s) according to the specific bit sequence(s) identified by the identifying unit 116. In one exemplary design, the determining unit 114 determines the updated bit sequences by performing a mapping operation upon the specific bit sequences. In another exemplary design, the determining unit 114 determines a new initial control gate voltage, and the control unit 112 refers to the new initial control gate voltage to control the flash memory 102 to output bit sequences having updated specific bit sequence(s) included therein.
[0054] Please refer to
[0055] As mentioned above, the flash memory 102 is capable of determining a hard bit value (i.e., CSB) of each of the memory cells M_0-M_K by the initial control gate voltages V.sub.CSB1 and V.sub.CSB2. Therefore, each of the bit sequences BS_0-BS_M has seven binary digits obtained due to the control gate voltages V.sub.CSB1, V.sub.CSB1+D, V.sub.CSB1−D, V.sub.CSB1+2D, V.sub.CSB1−2D, V.sub.CSB1+3D, V.sub.CSB1−3D, V.sub.CSB2, V.sub.CSB2−D, V.sub.CSB2+D, V.sub.CSB2−2D, V.sub.CSB2+2D, V.sub.CSB2−3D, and V.sub.CSB2+3D. Please note that each of the bit sequences BS_0-BS_M acts as a soft bit representative of the soft information read from a memory cell, and the binary digit obtained due to the initial control gate voltage V.sub.CSB1 or V.sub.CSB2 may serve as a sign bit (i.e., a hard bit value).
[0056] Similarly, each bit sequence may have one of eight possible binary digit combinations BS1-BS8. When the electrical charge currently stored on the floating gate of the memory cell makes the threshold voltage of the memory cell higher than V.sub.CSB2+3D or lower than V.sub.CSB1−3D, the bit sequence read from the memory cell would have the binary digit combination BS1=“1111111”. When the electrical charge currently stored on the floating gate of the memory cell makes the threshold voltage of the memory cell located between V.sub.CSB2+2D and V.sub.CSB2+3D or located between V.sub.CSB1−2D and V.sub.CSB1−3D, the bit sequence read from the memory cell would have the binary digit combination BS2=“1111110”. When the electrical charge currently stored on the floating gate of the memory cell makes the threshold voltage of the memory cell located between V.sub.CSB2+D and V.sub.CSB2+2D or located between V.sub.CSB1−D and V.sub.CSB1−2D, the bit sequence read from the memory cell would have the binary digit combination BS3=“1111010”. When the electrical charge currently stored on the floating gate of the memory cell makes the threshold voltage of the memory cell located between V.sub.CSB2 and V.sub.CSB2+D or located between V.sub.CSB1 and V.sub.CSB1−D, the bit sequence read from the memory cell would have the binary digit combination BS4=“1101010”. When the electrical charge currently stored on the floating gate of the memory cell makes the threshold voltage of the memory cell located between V.sub.CSB2−3D and V.sub.CSB1+3D, the bit sequence read from the memory cell would have the binary digit combination BS8=“0000000”. When the electrical charge currently stored on the floating gate of the memory cell makes the threshold voltage of the memory cell located between V.sub.CSB2−2D and V.sub.CSB2−3D or located between V.sub.CSB1+2D and V.sub.CSB1+3D, the bit sequence read from the memory cell would have the binary digit combination BS7=“0000010”. When the electrical charge currently stored on the floating gate of the memory cell makes the threshold voltage of the memory cell located between V.sub.CSB2−D and V.sub.CSB2−2D or located between V.sub.CSB1+D and V.sub.CSB1+2D, the bit sequence read from the memory cell would have the binary digit combination BS6=“0001010”. When the electrical charge currently stored on the floating gate of the memory cell makes the threshold voltage of the memory cell located between V.sub.CSB2 and V.sub.CSB2−D or located between V.sub.CSB1 and V.sub.CSB1+D, the bit sequence read from the memory cell would have the binary digit combination BS5=“0101010”.
[0057] When all of the binary digits included in a bit sequence are 1's, this means that the corresponding memory cell has the electrical charge level L0, L1, L6, or L7, and the reliability of CSB=1 may be high. When all of the binary digits included in a bit sequence are 0's, this means that the corresponding memory cell has the electrical charge level L2, L3, L4, or L5, and the reliability of CSB=0 may be high. However, when a bit sequence have different binary digits “0” and “1” included therein, this means that the corresponding memory cell has the electrical charge level L1, L2, L5, or L6. As the threshold voltage of the corresponding memory cell is located between V.sub.CSB1−3D and V.sub.CSB1+3D or located between V.sub.CSB2−3D and V.sub.CSB2+3D, the reliability of CSB=1/CSB=0 may be low due to the fact that the error probability may be high. Therefore, the bit sequences each having one of the binary digit combinations BS2-BS7 should be monitored to track the threshold voltage distribution variation around the initial control gate voltages V.sub.CSB1 and V.sub.CSB2 (i.e., the threshold voltage distribution variation between the electrical charge levels L1 and L2, and the threshold voltage distribution variation between the electrical charge levels L5 and L6).
[0058] The identifying unit 116 identifies specific bit sequences each having different binary digits “0” and “1” included therein. However, as the flash memory 102 simply outputs one bit sequence of a memory cell in response to seven read operations each utilizing two control gate voltages, the memory controller 104 does not know whether the bit sequence is generated from a memory cell having a threshold voltage between V.sub.CBS1+3D and V.sub.CSB1−3D or generated from a memory cell having a threshold voltage between V.sub.CBS2+3D and V.sub.CSB2−3D. For example, when the bit sequence BS_0 has the binary digit combination BS2 (i.e., “1111110”), the memory cell M_0 may have a threshold voltage located between V.sub.CSB2+2D and V.sub.CSB2+3D or located between V.sub.CSB1−2D and V.sub.CSB1−3D. Thus, to use the aforementioned threshold voltage distribution tracking mechanism employed for updating the specific bit sequences each having different binary digits “0” and “1” included therein, it is necessary to discriminate between a specific bit sequence generated from a memory cell having a threshold voltage located between V.sub.CSB1−3D and V.sub.CSB1+3D and a specific bit sequence generated from a memory cell having a threshold voltage located between V.sub.CSB2−3D and V.sub.CSB2+3D.
[0059] In one exemplary design, the identifying unit 116 identifies each specific bit sequence of a specific memory cell by further referring to identified bit(s) of the specific memory cell. For example, reading the LSB data of the memory cells M_0-M_K is performed prior to reading the CSB data of the memory cells M_0-M_K. Therefore, before the control unit 112 controls the flash memory 102 to output soft bits (i.e., soft information values) of the CSB data, the LSB bits of the memory cells M_0-M_K are known in advance. When finding a specific bit sequence with different binary digits included therein, the identifying unit 116 refers to an LSB bit of the specific memory cell which outputs the specific bit sequence to thereby identify whether the specific bit sequence is generated from the specific memory cell having a threshold voltage located between V.sub.CSB1−3D and V.sub.CSB1+3D or generated from the specific memory cell having a threshold voltage located between V.sub.CSB2−3D and V.sub.CSB2+3D.
[0060] As mentioned above, the determining unit 114 is arranged for determining an updated bit sequence of the at least one specific memory cell according to at least the specific bit sequence. By way of example, the determining unit 114 determines the updated bit sequence of the at least one specific memory cell by mapping the specific bit sequence to the updated bit sequence. In this exemplary design, the bit sequences BS_0-BS_K generated from the physical page P_0 are buffered in the storage device 108. When the ECC corrector 122 indicates that the bit sequences BS_0-BS_K include uncorrectable error bits, the identifying unit 116 is operative to monitor the bit sequences BS_0-BS_K and identify specific bit sequences each having different binary digits “0” and “1” included therein (i.e., specific bit sequences each having the binary digit combination BS2, BS3, BS4, BS5, BS6, or BS7). Specifically, with the help of identified bits (e.g., LSBs) of the memory cells M_0-M_K, the identifying unit 116 is capable of distinguish between specific bit sequences generated from specific memory cells each having a threshold voltage located between V.sub.CSB1−3D and V.sub.CSB1+3D and specific bit sequences generated from specific memory cells each having a threshold voltage located between V.sub.CSB2−3D and V.sub.CSB2+3D.
[0061] Next, the determining unit 114 determines a first mapping rule according to a first histogram derived from counting the specific bit sequences that are generated from identified specific memory cells each having a threshold voltage located between V.sub.CSB1−3D and V.sub.CSB1+3D, and also determines a second mapping rule according to a second histogram derived from counting identified specific bit sequences that are generated from specific memory cells each having a threshold voltage located between V.sub.CSB2−3D and V.sub.CSB2+3D. In addition, based on the first histogram, a new initial control gate voltage corresponding to a local minimum of the threshold voltage distribution corresponding to the electrical charge levels L1 and L2 can be found. Similarly, based on the second histogram, a new initial control gate voltage corresponding to a local minimum of the threshold voltage distribution corresponding to the electrical charge levels L5 and L6 can be found. After determining the first mapping rule, the determining unit 114 updates the specific bit sequences that are generated from identified specific memory cells each having a threshold voltage located between V.sub.CSB1−3D and V.sub.CSB1+3D. Similarly, after determining the second mapping rule, the determining unit 114 updates the specific bit sequences that are generated from identified specific memory cells each having a threshold voltage located between V.sub.CSB2−3D and V.sub.CSB2+3D. In this way, the error probability of the specific bit sequence is effectively lowered due to the adjustment made to the original binary digit combination. As a person skilled in the art can readily understand details directed to determining the first and second mapping rules and updating the specific bit sequences by the first and second mapping rules after reading above paragraphs pertinent to the example shown
[0062] Next, the bit sequences BS_0-BS_K with one or more bit sequences updated/adjusted by the determining unit 114 according to the first and second mapping rules are processed by the ECC circuit (e.g., an LDPC decoder) 110 again. As the number of error bits can be reduced by the determining unit 114 collaborating with the identifying unit 116, the ECC circuit 110 may have chance to successfully correct any error bits remaining in the currently processed readout information (i.e., soft information) of the physical page P_0. When the ECC corrector 122 indicates that the decoded result generated from the ECC circuit 110 is error-free, the read operation of reading CSB data of the memory cells M_0-M_K of the target physical page P_0 is accomplished. On the other hand, when the ECC corrector 122 indicates that the currently processed readout information still contains uncorrectable error bits, the determining unit 116 may further adjust the first and second mapping rules to try reducing the error probability of the specific bit sequence identified by the identifying unit 116.
[0063] In above exemplary embodiment, the determining unit 114 performs the mapping operation to update the specific bit sequences identified by the identifying unit 116. However, this is for illustrative purposes only, and is not meant to be a limitation of the present invention. In an alternative design, after the determining unit 144 determines that other control gate voltages different from V.sub.CSB1 and V.sub.CSB2 should be better control gate voltages for identifying CSBs of the memory cells M_0-M_K, the control unit 106 may be configured to set the initial control gate voltages by voltage values found using the first histogram and the second histogram, and then control the flash memory 102 to perform seven read operations upon each of the memory cells M_0-M_K according to the updated initial control gate voltages. Therefore, the flash memory 102 outputs new bit sequences BS_0-BS_M. Next, the ECC circuit 110 processes the new bit sequences BS_0-BS_M (i.e., an updated codeword read from the physical page P_0) to correct any error bits found in the new bit sequences BS_0-BS_M. As a person skilled in the art can readily understand related operation after reading above paragraphs, further description is omitted here for brevity.
[0064] Briefly summarized, in a case where each read operation utilizes more than one control gate voltage (e.g., two control gate voltages) applied to a control gate of each of the memory cells, and control gate voltages utilized by one read operation is different from control gate voltages utilized by another read operation, the identifying unit 116 is implemented for identifying any specific bit sequence having different binary digits included therein according to each identified bit of the specific memory cell which outputs the specific bit sequence, and the determining unit 114 is implemented for determining updated specific bit sequences according to the specific bit sequences identified by the identifying unit 116. In one exemplary design, the determining unit 114 determines the updated bit sequences by performing a mapping operation upon the specific bit sequences. In another exemplary design, the determining unit 114 determines new initial control gate voltages, and the control unit 112 refers to the new initial control gate voltages to control the flash memory 102 to output bit sequences having updated specific bit sequence(s) included therein.
[0065] Please refer to
[0066] As mentioned above, the flash memory 102 is capable of determining a hard bit value (i.e., MSB) of each of the memory cells M_0-M_K by the initial control gate voltages V.sub.MSB1, V.sub.MSB2, V.sub.MSB3, and V.sub.MSB4. Therefore, each of the bit sequences BS_0-BS_M has seven binary digits obtained due to the above-mentioned voltages. Please note that each of the bit sequences BS_0-BS_M acts as a soft bit representative of the soft information read from a memory cell, and the binary digit obtained due to the initial control gate voltage V.sub.MSB1, V.sub.MSB2, V.sub.MSB3, or V.sub.MSB4 may serve as a sign bit (i.e., a hard bit value).
[0067] Similarly, each bit sequence may have one of eight possible binary digit combinations BS1-BS8. When the electrical charge currently stored on the floating gate of the memory cell makes the threshold voltage of the memory cell higher than V.sub.MSB4+3D, lower than V.sub.MSB1−3D, or located between V.sub.MSB2+3D and V.sub.MSB3−3D, the bit sequence read from the memory cell would have the binary digit combination BS1=“1111111”. When the electrical charge currently stored on the floating gate of the memory cell makes the threshold voltage of the memory cell located between V.sub.MSB4+2D and V.sub.MSB2+3D, located between V.sub.MSB1−2D and V.sub.MSB1−3D, located between V.sub.MSB3−2D and V.sub.MSB3−3D, or located between V.sub.MSB2+2D and V.sub.MSB2+3D, the bit sequence read from the memory cell would have the binary digit combination BS2=“1111110”. When the electrical charge currently stored on the floating gate of the memory cell makes the threshold voltage of the memory cell located between V.sub.MSB4+D and V.sub.MSB4+2D, located between V.sub.MSB2+D and V.sub.MSB2+2D, located between V.sub.MSB1−D and V.sub.MSB1−2D, or located between V.sub.MSB3−D and V.sub.MSB3−2D, the bit sequence read from the memory cell would have the binary digit combination BS3=“1111010”. When the electrical charge currently stored on the floating gate of the memory cell makes the threshold voltage of the memory cell located between V.sub.MSB4 and V.sub.MSB4+D, located between V.sub.MSB2 and V.sub.MSB2+D, located between V.sub.MSB1 and V.sub.MSB1−D, or located between V.sub.MSB3 and V.sub.MSB3−D, the bit sequence read from the memory cell would have the binary digit combination BS4=“1101010”. When the electrical charge currently stored on the floating gate of the memory cell makes the threshold voltage of the memory cell located between V.sub.MSB4−3D and V.sub.MSB3+3D or located between V.sub.MSB2−3D and V.sub.MSB1+3D, the bit sequence read from the memory cell would have the binary digit combination BS8=“0000000”. When the electrical charge currently stored on the floating gate of the memory cell makes the threshold voltage of the memory cell located between V.sub.MSB4−2D and V.sub.MSB4−3D, located between V.sub.MSB2−2D and V.sub.MSB2−3D, located between V.sub.MSB1+2D and V.sub.MSB1+3D, or located between V.sub.MSB3+2D and V.sub.MSB3+3D, the bit sequence read from the memory cell would have the binary digit combination BS7=“0000010”. When the electrical charge currently stored on the floating gate of the memory cell makes the threshold voltage of the memory cell located between V.sub.MSB4−D and V.sub.MSB4−2D, located between V.sub.MSB2−D and V.sub.MSB2−2D, located between V.sub.MSB1+D and V.sub.MSB1+2D, or located between V.sub.MSB3+D and V.sub.MSB3+2D, the bit sequence read from the memory cell would have the binary digit combination BS6=“0001010”. When the electrical charge currently stored on the floating gate of the memory cell makes the threshold voltage of the memory cell located between V.sub.MSB4 and V.sub.MSB4−D, located between V.sub.MSB2 and V.sub.MSB2−D, located between V.sub.MSB1 and V.sub.MSB1+D, or located between V.sub.MSB3 and V.sub.MSB3+D, the bit sequence read from the memory cell would have the binary digit combination BS5=“0101010”.
[0068] When all of the binary digits included in a bit sequence are 1's, this means that the corresponding memory cell has the electrical charge level L0, L3, L4, or L7, and the reliability of MSB=1 may be high. When all of the binary digits included in a bit sequence are 0's, this means that the corresponding memory cell has the electrical charge level L1, L2, L5, or L6, and the reliability of MSB=0 may be high. However, when a bit sequence have different binary digits “0” and “1” included therein, this means that the corresponding memory cell has the electrical charge level being one of L0-L7. As the threshold voltage of the corresponding memory cell is located between V.sub.MSB1−3D and V.sub.MSB1+3D, located between V.sub.MSB2−3D and V.sub.MSB2+3D, located between V.sub.MSB3−3D and V.sub.MSB3+3D, or located between V.sub.MSB4−3D and V.sub.MSB4+3D, the reliability of MSB=1/MSB=0 may be low due to the fact that the error probability may be high. Therefore, the bit sequences each having one of the binary digit combinations BS2-BS7 should be monitored to track the threshold voltage distribution variation around the initial control gate voltages V.sub.MSB1-V.sub.MSB4 (i.e., the threshold voltage distribution variation between the electrical charge levels L0 and L1, the threshold voltage distribution variation between the electrical charge levels L2 and L3, the threshold voltage distribution variation between the electrical charge levels L4 and L5, and the threshold voltage distribution variation between the electrical charge levels L6 and L7).
[0069] Similarly, as the flash memory 102 simply outputs one bit sequence of a memory cell in response to seven read operations each utilizing four control gate voltages, it is necessary to discriminate among a specific bit sequence generated from a memory cell having a threshold voltage located between V.sub.MSB1−3D and V.sub.MSB1+3D, a specific bit sequence generated from a memory cell having a threshold voltage located between V.sub.MSB2−3D and V.sub.MSB2+3D, a specific bit sequence generated from a memory cell having a threshold voltage located between V.sub.MSB3−3D and V.sub.MSB3+3D, and a specific bit sequence generated from a memory cell having a threshold voltage located between V.sub.MSB4−3D and V.sub.MSB4+3D. In one exemplary design, the identifying unit 116 identifies each specific bit sequence of a specific memory cell by further referring to identified bit (s) of the specific memory cell. For example, reading the LSB data and CSB data of the memory cells M_0-M_K is performed prior to reading the MSB data of the memory cells M_0-M_K. Therefore, before the control unit 112 controls the flash memory 102 to output soft bits (i.e., soft information values) of the MSB data, the LSBs and CSBs of the memory cells M_0-M_K are known in advance and therefore can be utilized by the identifying unit 116 to identify whether the specific bit sequence is generated from the specific memory cell having a threshold voltage located between V.sub.MSB1−3D and V.sub.MSB1+3D, generated from the specific memory cell having a threshold voltage located between V.sub.MSB2−3D and V.sub.MSB2+3D, generated from the specific memory cell having a threshold voltage located between V.sub.MSB3−3D and V.sub.MSB3+3D, or generated from the specific memory cell having a threshold voltage located between V.sub.MSB4−3D and V.sub.MSB4+3D.
[0070] As mentioned above, the determining unit 114 is arranged for determining an updated bit sequence of the at least one specific memory cell according to at least the specific bit sequence. By way of example, the determining unit 114 determines the updated bit sequence of the at least one specific memory cell by mapping the specific bit sequence to the updated bit sequence. In this exemplary design, the bit sequences BS_0-BS_K generated from the physical page P_0 are buffered in the storage device 108. When the ECC corrector 122 indicates that the bit sequences BS_0-BS_K include uncorrectable error bits, the identifying unit 116 is operative to monitor the bit sequences BS_0-BS_K and identify specific bit sequences each having different binary digits “0” and “1” included therein (i.e., specific bit sequences each having the binary digit combination BS2, BS3, BS4, BS5, BS6, or BS7). Specifically, with the help of identified bits (e.g., LSBs and CSBs) of the memory cells M_0-M_K, the identifying unit 116 is capable of identifying specific bit sequences generated from specific memory cells each having a threshold voltage located between V.sub.MSB1−3D and V.sub.MSB1+3D, identifying specific bit sequences generated from specific memory cells each having a threshold voltage located between V.sub.MSB2−3D and V.sub.MSB2+3D, identifying specific bit sequences generated from specific memory cells each having a threshold voltage located between V.sub.MSB3−3D and V.sub.MSB3+3D, and identifying specific bit sequences generated from specific memory cells each having a threshold voltage located between V.sub.MSB4−3D and V.sub.MSB4+3D.
[0071] Next, the determining unit 114 determines a first mapping rule according to a first histogram derived from counting the specific bit sequences that are generated from identified specific memory cells each having a threshold voltage located between V.sub.MSB1−3D and V.sub.MSB1+3D, determines a second mapping rule according to a second histogram derived from counting identified specific bit sequences that are generated from specific memory cells each having a threshold voltage located between V.sub.MSB2−3D and V.sub.MSB2+3D, determines a third mapping rule according to a third histogram derived from counting identified specific bit sequences that are generated from specific memory cells each having a threshold voltage located between V.sub.MSB3−3D and V.sub.MSB3+3D, and determines a fourth mapping rule according to a fourth histogram derived from counting identified specific bit sequences that are generated from specific memory cells each having a threshold voltage located between V.sub.MSB4−3D and V.sub.MSB4+3D.
[0072] As a person skilled in the art can readily understand details of reading MSB data from the memory cells after reading above paragraphs illustrating details of reading CSB data from the memory cells, further description is omitted here for brevity.
[0073] Briefly summarized, in a case where each read operation utilizes more than one control gate voltage (e.g., four control gate voltages) applied to a control gate of each of the memory cells, and control gate voltages utilized by one read operation is different from control gate voltages utilized by another read operation, the identifying unit 116 is implemented for identifying any specific bit sequence having different binary digits included therein according to each identified bit of the specific memory cell which outputs the specific bit sequence, and the determining unit 114 is implemented for determining updated specific bit sequences according to the specific bit sequences identified by the identifying unit 116. In one exemplary design, the determining unit 114 determines the updated bit sequences by performing a mapping operation upon the specific bit sequences. In another exemplary design, the determining unit 114 determines new initial control gate voltages, and the control unit 112 refers to the new initial control gate voltages to control the flash memory 102 to output bit sequences having updated specific bit sequence(s) included therein.
[0074] As mentioned above, when reading soft information of the CSB data stored in the memory cells, the LSBs of the memory cells are used by the identifying unit 116 to discriminate between specific bit sequences that are generated from memory cells each having a threshold voltage located between V.sub.CSB1−3D and V.sub.CSB1+3D and specific bit sequences that are generated from memory cells each having a threshold voltage located between V.sub.CSB2−3D and V.sub.CSB2+3D. Thus, the step of reading the soft information of the LSB data is required to be performed before the step of reading the soft information of the CSB data. However, in an alternative design, the identifying unit 116 is capable of discriminating between specific bit sequences without referring to the identified bits (e.g., LSBs) of the memory cells. Please refer to
[0075] As shown in sub-diagram (B) of
[0076] Therefore, when a first bit sequence generated from first read operations using control gate voltages set according to different voltage adjusting orders (e.g., OD1 and OD2) is identical to a second bit sequence generated from second read operations using control gate voltages set by the same voltage adjusting order (e.g., OD1), the identifying unit 116 knows that the first bit sequence/second bit sequence is generated from a memory cell having a threshold voltage located between V.sub.CSB1−3D and V.sub.CSB1+3D. When the first bit sequence generated from first read operations using control gate voltages set according to different voltage adjusting orders (e.g., OD1 and OD2) is different from the second bit sequence generated from second read operations using control gate voltages set by the same voltage adjusting order (e.g., OD1), the identifying unit 116 knows that the first bit sequence/second bit sequence is generated from a memory cell having a threshold voltage located between V.sub.CSB2−3D and V.sub.CSB2+3D.
[0077] To put it simply, the control unit 112 of the control logic 106 controls the flash memory 102 to perform a plurality of read operations upon each of the memory cells of one physical page for obtaining soft bits of the memory cells, wherein the read operations include first read operations and second read operations each utilizing two control gate voltages applied to a control gate of each memory cell. The two control gate voltages utilized by one of the first read operations are different from the two control gate voltages utilized by another of the first read operations, one of the two control gate voltages utilized in each of the first read operations is set according to a first voltage adjusting order, the other of the two control gate voltages utilized in each of the first read operations is set according to a second voltage adjusting order different from the first voltage adjusting order. Besides, the two control gate voltages utilized by one of the second read operations are different from the two control gate voltages utilized by another of the second read operations, one of the two control gate voltages utilized in each of the second read operations is set according to the first voltage adjusting order, and the other of the two control gate voltages utilized in each of the second read operations is set according to the first voltage adjusting order. The identifying unit 116 of the control logic 106 identifies a specific bit sequence with different binary digits included therein by referring to a first bit sequence read from a specific memory cell by the first read operations and a second bit sequence read from the specific memory cell by the second read operations. After the specific bit sequences, each having different binary digits included therein, are correctly categorized by the identifying unit 116, the determining unit 114 can employ the aforementioned procedure to determine the updated bit sequences correctly.
[0078] The read operations shown in sub-diagram (A) of
[0079] The read operations shown in sub-diagram (B) of
[0080] Please refer to
[0081] The memory controller 904 is implemented to control access (read/write) of the flash memory 102. In this exemplary embodiment, the memory controller 904 includes, but is not limited to, a control logic 906 having a control unit 912, a counting unit 914, and a comparing unit 916 included therein, a receiving circuit 908 having a storage device (e.g., a memory device) 918, and an ECC circuit 910 having an ECC detector 920 and an ECC corrector 922 included therein. Please note that only the elements pertinent to the technical features of the present invention are shown in
[0082] In this exemplary embodiment, the ECC circuit 910 may be a Bose-Chaudhuri-Hocquenghem (BCH) decoder. The control logic 906 is arranged for controlling the flash memory 102 to perform a plurality of read operations upon each of the memory cells M_0-M_K of the target physical page P_0, and determining readout information of the memory cells M_0-M_K according to binary digit distribution characteristics of bit sequences BS_0-BS_K. The read operations include at least a first read operation, a second read operation, and a third read operation used for determining control gate voltage shifting direction (s) used for finding better control gate voltage (s). Further details are described as below.
[0083] Please refer to
[0084] Next, the control unit 912 updates the current control gate voltage V.sub.LSB′ employed by the second read operation by V8 which is higher than V7, and then controls the flash memory to perform the third read operation upon memory cells M_0-M_K according to the updated control gate voltage V.sub.LSB″. Thus, a third codeword CW_3 consisted of third bits of the bit sequences BS_0-BS_K is received by the receiving circuit 908. Please note that the first codeword CW_1 originally buffered in the storage device 918 will be overwritten by the second codeword CW_2; additionally, bits of the second codeword CW_2 buffered in the storage device 918 are transmitted to the comparing unit 916 one by one before overwritten by the incoming bits of the third codeword CW_3. The comparing unit 916 is further arranged for comparing bits of the second codeword CW_2 (i.e., second bits of the bit sequences BS_0-BS_K) and bits of the third codeword CW_3 (i.e., third bits of the bit sequences BS_0-BS_K). The comparison result will indicate which bit position has the second bit flipping due to a transition from the second binary digit (e.g., “0”) to the first binary digit (e.g., “1”). The counting unit 914 is further arranged for counting the number of second bit flipping between the second codeword CW_2 and the third codeword CW_3. That is, the counting unit 914 generates a second counter number N2 by counting the number of second bit flipping between second bits and third bits of the bit sequences BS_0-BS_K, wherein one second bit flipping occurs when the second bit and the third bit of one bit sequence have the second binary digit (e.g., “0”) and the first binary digit (e.g., “1”), respectively.
[0085] After receiving the first counter number N1 and the second counter number N2 generated from the counting unit 914, the control unit 912 determines the readout information which can pass the ECC parity check by referring to the first counter number N1 and the second counter number N2. For example, the control unit 912 determines the shifting direction DS of the control gate voltage according to the first counter number N1 and the second counter number N2. More specifically, as can be seen from
[0086] After the shifting direction DS is determined, the control logic 912 determines a new control gate voltage according to the shifting direction DS. When the readout information (i.e., a new codeword) obtained from applying the new control gate voltage to the control gate of each of the memory cells M_0-M_K of the target physical page P_0 passes the ECC parity check, this implies that the codeword processed by the ECC circuit 110 will become error-free. As the LSB data is successfully determined by the control unit 912 which updates the control gate voltage according to the shifting direction DS, the control unit 912 records the currently used control gate voltage as an initial control gate voltage to be used by the next LSB read operation performed upon the physical page P_0.
[0087] However, when the readout information (i.e., a new codeword) obtained from applying the new control gate voltage to the control gate of each of the memory cells M_0-M_K of the physical page P_0 fails to pass the ECC parity check, this implies that the codeword processed by the ECC circuit 110 still contains uncorrectable error bits, the control logic 912 will determine another control gate voltage according to the shifting direction DS. Updating the control gate voltage according to the shifting direction DS is not stopped until the codeword is error-free or all of the error bits presented in the codeword are correctable. Please note that the ECC circuit (e.g., a BCH decoder) 100 has error correction capability. Therefore, the control unit 912 is not required to exactly shift the control gate voltage to the optimum value V5 according to the shifting direction DS.
[0088] In above exemplary embodiment, the control unit 912 controls the flash memory 102 to perform the first read operation which utilizes the initial control gate voltage V.sub.LSB, the second read operation which utilizes the lower control gate voltage V.sub.LSB′, and the third read operation which utilizes the higher control gate voltage V.sub.LSB″, sequentially. Therefore, the initial control gate voltage V.sub.LSB, the lower control gate voltage V.sub.LSB′ and the higher control gate voltage V.sub.LSB″ are applied to the control gate of each of the memory cells M_0-M_K, sequentially. However, this is for illustrative purposes only, and is not meant to be a limitation of the present invention.
[0089] Please refer to
[0090] Similarly, when the initial control gate voltage V.sub.LSB is set to V7 by the control unit 912 and the flash memory 102 performs the first read operation upon memory cells M_0-M_K according to the initial control gate voltage V.sub.LSB, the number of error bits presented in the readout information (i.e., a first codeword CW_1 consisted of first bits of the bit sequences BS_0-BS_K) exceeds the maximum number of error bits that can be corrected by the ECC circuit 910. Thus, the threshold voltage distribution tracking mechanism is enabled accordingly. Next, the control unit 912 updates the initial control gate voltage V.sub.LSB employed by the first read operation by V8 which is higher than V7, and then controls the flash memory 102 to perform the second read operation upon memory cells M_0-M_K according to the updated control gate voltage V.sub.LSB″. Thus, a second codeword CW_2′ consisted of second bits of the bit sequences BS_0-BS_K is received by the receiving circuit 908. The comparing unit 916 compares bits of the first codeword CW_1 (i.e., first bits of the bit sequences BS_0-BS_K) and bits of the second codeword CW_2′ (i.e., second bits of the bit sequences BS_0-BS_K). The comparison result will indicate which bit position has the first bit flipping due to a transition from a first binary digit (e.g., “0”) to a second binary digit (e.g., “1”). The counting unit 914 counts the number of first bit flipping between the first codeword CW_1 and the second codeword CW_2′ to thereby obtain a first counter number N1′. Next, the control unit 912 updates the current control gate voltage V.sub.LSB″ employed by the second read operation by V6 which is lower than V7, and then controls the flash memory 102 to perform the third read operation upon memory cells M_0-M_K according to the updated control gate voltage V.sub.LSB′. Thus, a third codeword CW_3′ consisted of third bits of the bit sequences BS_0-BS_K is received by the receiving circuit 908. The comparing unit 916 compares bits of the second codeword CW_2′ (i.e., second bits of the bit sequences BS_0-BS_K) and bits of the third codeword CW_3′ (i.e., third bits of the bit sequences BS_0-BS_K). The comparison result will indicate which bit position has the second bit flipping due to a transition from the second binary digit (e.g., “1”) to the first binary digit (e.g., “0”). The counting unit 914 counts the number of second bit flipping between the second codeword CW_2′ and the third codeword CW_3′ to thereby obtain a second counter number N2′. As can be seen from
[0091] The operation of finding the best control gate voltage (s) used for reading the CSB data is detailed as follows. Please refer to
[0092] When the best location of the control gate voltage (i.e., VT_6′) has been found by the shifting direction DS2 and the ECC corrector 922 still indicates that the readout information obtained from using the best control gate voltage VT_6′ and the initial control gate voltage V.sub.CSB1 has uncorrectable errors, the control unit 912 keeps the best control gate voltage VT_6′ intact, and starts updating the control gate voltage V.sub.CSB1 to find the shifting direction DS1. Please refer to
[0093] In above examples shown in
[0094] The comparing unit 916 compares the first bits and the second bits of the bit sequences BS_0-BS_K, wherein a first codeword CW_11 consisted of the first bits of the bit sequences BS_0-BS_K is obtained by the first read operation, and a second codeword CW_21 consisted of the second bits of the bit sequences BS_0-BS_K is are obtained by the second read operation. The comparison result will indicate which bit position has one first bit flipping due to a transition from a first binary digit (e.g., “1”) to a second binary digit (e.g., “0”), and further indicate which bit position has one second bit flipping due to a transition from the second binary digit (e.g., “0”) to the first binary digit (e.g., “1”). Please note that, in this exemplary embodiment, the first bit flipping is resulted from shifting the control gate voltage from V.sub.CSB1 to V.sub.CSB1′, and the second bit flipping is resulted from shifting the control gate voltage from V.sub.CSB2 to V.sub.CSB2′. The counting unit 914 counts the number of first bit flipping between the first codeword CW_11 and the second codeword CW_21, and also counts the number of second bit flipping between the first codeword CW_11 and the second codeword CW_21. That is, the counting unit 914 generates a first counter number N1 by counting the number of first bit flipping between first bits and second bits of the bit sequences BS_0-BS_K, and generates a second counter number N2 by counting the number of second bit flipping between first bits and second bits of the bit sequences BS_0-BS_K, wherein one first bit flipping occurs when the first bit and the second bit of one bit sequence have the first binary digit (e.g., “1”) and the second binary digit (e.g., “0”), respectively, and one second bit flipping occurs when the first bit and the second bit of one bit sequence have the second binary digit (e.g., “0”) and the first binary digit (e.g., “1”), respectively.
[0095] Besides, the comparing unit 916 compares the second bits and the third bits of the bit sequences BS_0-BS_K, wherein a third codeword CW_31 consisted of the third bits of the bit sequences BS_0-BS_K is obtained by the third read operation. The comparison result will indicate which bit position has one third bit flipping due to a transition from the second binary digit (e.g., “0”) to the first binary digit (e.g., “1”), and further indicate which bit position has one fourth bit flipping due to a transition from the first binary digit (e.g., “1”) to the second binary digit (e.g., “0”). Please note that, in this exemplary embodiment, the third bit flipping is resulted from shifting the control gate voltage from V.sub.CSB1′ to V.sub.CSB1″, and the fourth bit flipping is resulted from shifting the control gate voltage from V.sub.CSB2′ to V.sub.CSB2″. The counting unit 914 counts the number of third bit flipping between the second codeword CW_21 and the third codeword CW_31, and also counts the number of fourth bit flipping between the second codeword CW_21 and the third codeword CW_31. That is, the counting unit 914 generates a third counter number N3 by counting the number of third bit flipping between second bits and third bits of the bit sequences BS_0-BS_K, and generates a fourth counter number N4 by counting the number of fourth bit flipping between second bits and third bits of the bit sequences BS_0-BS_K, wherein one third bit flipping occurs when the second bit and the third bit of one bit sequence have the second binary digit (e.g., “0”) and the first binary digit (e.g., “1”), respectively, and one fourth bit flipping occurs when the second bit and the third bit of one bit sequence have the first binary digit (e.g., “1”) and the second binary digit (e.g., “0”), respectively.
[0096] After receiving the first counter number N1, the second counter number N2, the third counter number N3, and the fourth counter number N4 generated from the counting unit 914, the control unit 912 is capable of determining the shifting direction DS1 of one control gate voltage according to the first and third counter numbers N1 and N3, and determining the shifting direction DS2 of the other control gate voltage according to the second and fourth counter numbers N2 and N4. More specifically, the first counter number N1 represents the total number of 0's newly identified due to shifting the control gate voltage from V.sub.CSB1 to V.sub.CSB1′, the second counter number N2 represents the total number of 1's newly identified due to shifting the control gate voltage from V.sub.CSB2 to V.sub.CSB2′. Thus, the value (N3−N1) is representative of a total number of newly identified 1's resulted from shifting the control gate voltage from V.sub.CSB1 to V.sub.CSB1″, and the value (N4−N2) is representative of a total number of newly identified 0's resulted from shifting the control gate voltage from V.sub.CSB2 to V.sub.CSB2″ In this exemplary embodiment, (N3−N1) is greater than N1 and (N4−N2) is greater than N2, this implies that the local minimum of the threshold voltage distribution corresponding to the electrical charge levels L1 and L2 is located on a left side of the initial control gate voltage V.sub.CSB1, and the local minimum of the threshold voltage distribution corresponding to the electrical charge levels L5 and L6 is located on a left side of the initial control gate voltage V.sub.CSB2. Based on such an observation, the control unit 912 decides the shifting directions DS1 and DS2 simultaneously. Next, based on one or both of the shifting directions DS1 and DS2, the control unit 912 updates one or both of the control gate voltages to make the flash memory 102 generate readout information (i.e., CSBs) capable of passing the ECC parity check. As a person skilled in the art can readily understand the related operation after reading above paragraphs, further description is omitted here fore brevity.
[0097] In above exemplary embodiment, the control unit 912 controls the flash memory 102 to perform the first read operation which utilizes the initial control gate voltages V.sub.CSB1 and V.sub.CSB2, the second read operation which utilizes the control gate voltages V.sub.CSB1′ and V.sub.CSB2′, and the third read operation which utilizes the control gate voltages V.sub.CSB1″ and V.sub.CSB2″, sequentially. However, this is for illustrative purposes only, and is not meant to be a limitation of the present invention. In an alternative design, the control unit 912 is allowed to control the flash memory 102 to perform the first read operation which utilizes the initial control gate voltages V.sub.CSB1 and V.sub.CSB2, the second read operation which utilizes the control gate voltages V.sub.CSB1″ and V.sub.CSB2″, and the third read operation which utilizes the control gate voltages V.sub.CSB1′ and V.sub.CSB2′, sequentially. The same objective of determining the shifting directions DS1 and DS2 in a parallel processing manner is achieved. As a person skilled in the art can readily understand details of such an alternative design of determining shifting directions DS1 and DS2 after reading above paragraphs directed to the example of determining the shifting direction DS as shown in
[0098] Regarding the case of reading MSBs of the memory cells M_0-M_K of the target physical page P_0, it is similar to the case of reading CSBs of the memory cells M_0-M_K as mentioned above. The major difference is that each read operation for reading the MSBs requires four control gate voltages rather than two control gate voltages. As mentioned above, reading MSBs of memory cells M_0-M_K of the target physical page P_0 requires four control gate voltages V.sub.MSB1, V.sub.MSB2, V.sub.MSB3, and V.sub.MSB4. When the readout information of the physical page P_0 fails to pass the ECC parity check, it means that the MSBs read from the memory cells M_0-M_K include uncorrectable error bits. Thus, the threshold voltage distribution tracking mechanism is enabled to find better control gate voltage (s) used for reading the MSB data. In one exemplary embodiment, one of the control gate voltages V.sub.MSB1-V.sub.MSB4 is adjusted by the control unit 912 to find the shifting direction of one control gate voltage, while the remaining voltages of the control gate voltages V.sub.MSB1-V.sub.MSB4 are not adjusted by the control unit 912. Please refer to
[0099] Please refer to
[0100] Please refer to
[0101] Please refer to
[0102] As a person skilled in the art can readily understand detailed operations of determining the shifting direction DS4/DS3/DS2/DS1 and finding an updated control gate voltage according to the determined shifting direction DS4/DS3/DS2/DS1 after reading above paragraphs pertinent to the examples shown in
[0103] In above examples shown in
[0104] When the best locations of the control gate voltages (i.e., VT_5′ and VT_7′) have been found by the shifting directions DS3 and DS4, and the ECC corrector 922 still indicates that the readout information obtained from using the best control gate voltages VT_7′, VT_5′ and the initial control gate voltages V.sub.MSB1 and V.sub.MSB2 has uncorrectable errors, the control unit 912 keeps the best control gate voltages VT_7′ and VT_5′ intact, and starts updating the remaining two control gate voltages V.sub.MSB1 and V.sub.MSB2 to find other shifting directions DS1 and DS2 in a parallel processing manner.
[0105] Please refer to
[0106] As a person skilled in the art can readily understand detailed operations of determining multiple shifting direction DS4 and DS3 (DS2 and DS1) and finding updated control gate voltages according to the determined shifting directions DS4 and DS3 (DS2 and DS1) after reading above paragraphs pertinent to the examples shown in
[0107] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.