Semiconductor device and method for manufacturing same

Abstract

A semiconductor device includes at least one thin film transistor (100, 200), the at least one thin film transistor including a semiconductor layer (3A, 3B) which includes a channel region (31A, 31), a high-concentration impurity region, and a low-concentration impurity region (32A, 32B) which is located between the channel region and the high-concentration impurity region, a gate electrode (7A, 7B) provided on a gate insulating layer (5), an interlayer insulating layer (11) provided on the gate electrode, and a source electrode (8A, 8B) and a drain electrode (9A, 9B), wherein the interlayer insulating layer and the gate insulating layer have a contact hole extending to the semiconductor layer, at least one of the source electrode (8A, 8B) and the drain electrode (9A, 9B) being in contact with the high-concentration impurity region inside the contact hole, at a side wall of the contact hole, a side surface of the gate insulating layer is aligned with a side surface of the interlayer insulating layer, and at an upper surface of the semiconductor layer, an edge of the contact hole aligned with an edge of the high-concentration impurity region.

Claims

1. A semiconductor device comprising at least one thin film transistor on a substrate, the at least one thin film transistor including a semiconductor layer which includes a channel region, a high-concentration impurity region containing a first conductivity type impurity, and a low-concentration impurity region which is located between the channel region and the high-concentration impurity region, the low-concentration impurity region containing the first conductivity type impurity at a concentration lower than in the high-concentration impurity region and higher than in the channel region, a gate insulating layer provided on the semiconductor layer, a gate electrode provided on the gate insulating layer and arranged so as to extend over at least the channel region, an interlayer insulating layer provided on the gate electrode and the gate insulating layer, and a source electrode and a drain electrode which are coupled with the semiconductor layer, wherein the interlayer insulating layer and the gate insulating layer have a contact hole extending to the semiconductor layer, at least one of the source electrode and the drain electrode being provided on the interlayer insulating layer and in the contact hole and being in contact with the high-concentration impurity region inside the contact hole, at a side wall of the contact hole, a side surface of the gate insulating layer is aligned with a side surface of the interlayer insulating layer, at an upper surface of the semiconductor layer, an edge of the contact hole is aligned with an edge of the high-concentration impurity region, the at least one thin film transistor includes a first thin film transistor, in the first thin film transistor, the low-concentration impurity region includes a first low-concentration impurity region which is in contact with the high-concentration impurity region and a second low-concentration impurity region which is closer to the channel region than the first low-concentration impurity region, the first low-concentration impurity region contains the first conductivity type impurity at a concentration higher than in the second low-concentration impurity region, the entire low-concentration impurity region in the first thin film transistor does not overlap the gate electrode when viewed in a direction normal to the substrate, and in the first thin film transistor, an edge of the low-concentration impurity region which is on the channel region side is located in a same location as a part of an edge of the gate electrode in a direction perpendicular to the normal direction, when viewed in the normal direction.

2. The semiconductor device of claim 1, wherein the high-concentration impurity region is located inside the low-concentration impurity region when viewed in a direction normal to the substrate.

3. The semiconductor device of claim 1, wherein the at least one thin film transistor includes a second thin film transistor, in the second thin film transistor, a part of the low-concentration impurity region is covered with the gate electrode with the gate insulating layer interposed therebetween, in the second thin film transistor, the low-concentration impurity region includes a third low-concentration impurity region which is in contact with the high-concentration impurity region and a fourth low-concentration impurity region which is closer to the channel region than the third low-concentration impurity region, the third low-concentration impurity region contains the first conductivity type impurity at a concentration higher than in the fourth low-concentration impurity region and does not overlap the gate electrode when viewed in the normal direction, and the fourth low-concentration impurity region overlaps the gate electrode when viewed in the normal direction.

4. The semiconductor device of claim 3, wherein the first low-concentration impurity region of the first thin film transistor and the third low-concentration impurity region of the second thin film transistor contain a same impurity element, and the first and third low-concentration impurity regions have substantially equal concentration profiles of the first conductivity type impurity in a thickness direction.

5. The semiconductor device of claim 1, further comprising another thin film transistor which has a different conductivity type from that of the at least one thin film transistor, wherein the another thin film transistor includes another semiconductor layer including a channel region, a contact region, and another high-concentration impurity region which is located between the channel region and the contact region and which contains a second conductivity type impurity, the contact region containing the second conductivity type impurity at a same concentration as the another high concentration impurity region and containing the first conductivity type impurity at a concentration higher than the another high concentration impurity region, the gate insulating layer extending over the another semiconductor layer, another gate electrode provided on the gate insulating layer, the interlayer insulating layer extending over the another gate electrode and the gate insulating layer, and another source electrode and another drain electrode which are coupled with the another semiconductor layer, the interlayer insulating layer and the gate insulating layer have another contact hole extending to the another semiconductor layer, at least one of the another source electrode and the another drain electrode being provided on the interlayer insulating layer and in the another contact hole and being in contact with the contact region inside the another contact hole, at a side wall of the another contact hole, a side surface of the gate insulating layer is aligned with a side surface of the interlayer insulating layer, and at an upper surface of the another semiconductor layer, an edge of the another contact hole is aligned with an edge of the contact region.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIGS. 1 (a) and (b) are schematic cross-sectional views illustrating an LDD structure TFT 100 and a GOLD structure TFT 200, respectively, in a semiconductor device of the first embodiment.

(2) FIGS. 2 (a) and (b) are schematic plan illustrating semiconductor layers 3A, 3B in the LDD structure TFT 100 and the GOLD structure TFT 200, respectively.

(3) FIG. 3 (a) to (d) are schematic stepwise cross-sectional views illustrating an example of a method for forming the LDD structure TFT 100.

(4) FIG. 4 (a) to (d) are schematic stepwise cross-sectional views illustrating an example of a method for forming the TFT 200 that has a GOLD structure.

(5) FIG. 5 (a) is a cross-sectional view illustrating an LDD structure TFT 101 and a GOLD structure TFT 201 in a semiconductor device of the second embodiment (b) and (c) are plan views illustrating semiconductor layers 3A, 3B of the LDD structure TFT 101 and the GOLD structure TFT 201, respectively.

(6) FIG. 6 (a) to (e) are schematic stepwise cross-sectional views illustrating a method for manufacturing a semiconductor device of the second embodiment.

(7) FIG. 7 (a) is a process flow for forming a GOLD structure TFT 2000 of a reference example (b) is a process flow for forming the GOLD structure TFTs 200, 201.

(8) FIG. 8 (a) is a cross-sectional view of a p-type TFT 302 in the third embodiment. (b) is a plan view of a semiconductor layer 3C of the p-type TFT 302.

(9) FIG. 9 (a) to (f) are schematic stepwise cross-sectional views illustrating a method for manufacturing a semiconductor device of the third embodiment.

(10) FIG. 10 (a) is a cross-sectional view illustrating an LDD structure TFT 1000 and a GOLD structure TFT 2000 of a reference example (b) and (c) are top views of semiconductor layers 3D, 3E of the LDD structure TFT 1000 and the GOLD structure TFT 2000, respectively.

DESCRIPTION OF EMBODIMENTS

First Embodiment

(11) Hereinafter, an embodiment of the semiconductor device of the present invention is describes with reference to the drawings. In this specification, the semiconductor device widely includes substrates which include functional circuits, active matrix substrates, and display devices, such as liquid crystal display devices, organic EL display devices, etc.

(12) The semiconductor device of the present embodiment includes a substrate and a plurality of TFTs formed on the substrate. The plurality of TFTs include at least one TFT which has an LDD region. The TFT which has an LDD region may be an LDD structure TFT or may be a GOLD structure TFT. Alternatively, the TFT which has an LDD region may include both a GOLD structure TFT and an LDD structure TFT which are formed using a common semiconductor film.

(13) FIGS. 1(a) and 1(b) are schematic cross-sectional illustrating a TFT which has an LDD region in a semiconductor device of the present embodiment. FIG. 1(a) illustrates an LDD structure TFT 100. FIG. 1(b) illustrates a GOLD structure TFT 200. FIGS. 2(a) and 2(b) are schematic plan views illustrating semiconductor layers in the LDD structure TFT 100 and the GOLD structure TFT 200, respectively. In FIG. 1 and FIG. 2, like components are designated by the same reference marks or by reference marks including the same numeral. Some of the components of the LDD structure TFT 100 are designated by numerals suffixed with A. Some of the components of the GOLD structure TFT 200 are designated by numerals suffixed with B.

(14) As shown in FIG. 1(a), the LDD structure TFT 100 includes a semiconductor layer 3A formed on the substrate 1, a gate insulating layer 5 covering the semiconductor layer 3A, a gate electrode 7A formed on the gate insulating layer 5, an interlayer insulating layer 11 covering the gate electrode 7A and the semiconductor layer 3A, and a source electrode 8A and a drain electrode 9A which are electrically coupled with the semiconductor layer 3A.

(15) The semiconductor layer 3A includes a channel region 31A, a source region 33sA, a drain region 33dA and an LDD region 32A. The channel region 31A is located between the source region 33sA and the drain region 33dA. The LDD region 32A is located between the channel region 31A and at least one of the source region 33sA and the drain region 33dA. In this example, the source region 33sA and the drain region 33dA are first conductivity type regions containing a first conductivity type impurity (e.g., n-type impurity), for example, n.sup.+ type regions. The LDD region 32A is a first conductivity type region which contains a first conductivity type impurity (e.g., n-type impurity) at a concentration higher than in the channel region 31A but lower than in the source region 33sA and the drain region 33dA, for example, n.sup. type region. In this specification, the source region 33sA and the drain region 33dA are also generically referred to as high-concentration impurity region or n.sup.+ type region, and the LDD region 32A is also referred to as low-concentration impurity region or n.sup. type region.

(16) The gate electrode 7A is arranged so as to extend over at least the channel region 31A of the semiconductor layer 3A with the gate insulating layer 5 interposed therebetween. In this example, when viewed in the normal direction of the substrate 1, the gate electrode 7A extends over the channel region 31A but does not extend over any of the source region 33sA, the drain region 33dA and the LDD region 32A. When viewed in the normal direction of the substrate 1, an edge of the gate electrode 7A is aligned with an edge of the LDD region 32A on the channel region 31A side.

(17) The gate insulating layer 5 and the interlayer insulating layer 11 have a source contact hole 13A extending to the source region 33sA of the semiconductor layer 3A and a drain contact hole 14A extending to the drain region 33dA of the semiconductor layer 3A. These contact holes 13A, 14A are formed by simultaneously etching the gate insulating layer 5 and the interlayer insulating layer 11. Therefore, at the side walls of the source contact hole 13A and the drain contact hole 14A, the side surface of the gate insulating layer 5 is aligned with the side surface of the interlayer insulating layer 11.

(18) The source electrode 8A is provided on the inter layer insulating layer 11 and in the source contact hole 13A. The source electrode 8A is in contact with the source region 33sA inside the source contact hole 13A. The drain electrode 9A is provided on the interlayer insulating layer 11 and in the drain contact hole 14A. The drain electrode 9A is in contact with the drain region 33dA inside the drain contact hole 14A.

(19) In the present embodiment, the source region 33sA and the drain region 33dA are formed by implanting the first conductivity type impurity into the semiconductor layer 3A via the contact holes 13A, 14A. In this specification, an implantation step via a contact hole is referred to as contact doping step. Therefore, at the upper surface of the semiconductor layer 3A, the edge of the source contact hole 13A is aligned with the source region 33sA of the semiconductor layer 3A. Likewise, the edge of the drain contact hole 14A is aligned with the drain region 33dA of the semiconductor layer 3A. Here, the term in alignment only requires formation by implantation via a contact hole such as described above and includes a case where, for example, the first conductivity type impurity implanted into the semiconductor layer 3A is diffused into surroundings activation annealing. In such a configuration, a surface of the source electrode 8A which is in contact with the semiconductor layer 3A (contact surface) is aligned with the source region 33sA, and a surface of the drain electrode 9A which is in contact with the semiconductor layer 3A is aligned with the drain region 33dA.

(20) On the other hand, the GOLD structure TFT 200 shown in FIG. 1(b) includes a semiconductor layer 3B formed on the substrate 1, a gate insulating layer 5 covering the semiconductor layer 3B, a gate electrode 7B formed on the gate insulating layer 5, an interlayer insulating layer 11 covering the gate electrode 7B and the semiconductor layer 3B, and a source electrode 8B and a drain electrode 9B which are electrically coupled with the semiconductor layer 3B. The semiconductor layer 3B includes a channel region 31B, a source region 33s3, a drain region 33dB, and an LDD region 32B. The LDD region 32B is located between the channel region 31B and at least one of the source region 33sB and the drain region 33dB. The LDD region 32B contains the first conductivity type impurity at a concentration higher than in the channel region 318 but lower than in the source region 33sB and the drain region 33dB (hereinafter, high-concentration impurity regions).

(21) The GOLD structure TFT 200 is different from the LDD structure TFT 100 in that the gate electrode 7B is arranged so as to extend over not only the channel region 31B of the semiconductor layer 3B but also part of the LDD region. 32B with the gate insulating layer 5 interposed therebetween. The LDD region 32B includes portion which does not overlap the gate electrode 7B, i.e., portion which s located between the source and drain regions 33s8, 33dB and the gate electrode 7B (LDD portion 32(1)) when viewed in the normal direction of the substrate 1 and a portion overlapping the gate electrode 7B (hereinafter, GOLD portion 32(2)). The GOLD portion 32(2) is also referred to as GOLD region or NM region. The LDD portion 32(1) and the GOLD portion 32(2) may contain the impurity element at the same concentration or at different concentrations. As will be described later, the LDD portion 32(1) may contain the first conductivity type impurity at a higher concentration than in the GOLD portion 32(2).

(22) The other components are the same as those of the LDD structure TFT 100 shown in FIG. 1(a) and, therefore, the description thereof is herein omitted.

(23) Also in the GOLD structure TFT 200, the source region 33sB and the drain region 33dB are formed by implanting the first conductivity type Impurity into the semiconductor layer 3B via a source contact hole 13B and a drain contact hole 14B, respectively, as in the LDD structure TFT 100 (contact doping step). Therefore at the upper surface of the semiconductor layer 3B, the edges of the contact holes 13B, 14B are aligned with the edges of the source region 33sB and the drain region 33dB of the semiconductor layer 3B.

(24) The semiconductor device of the present embodiment may include both the LDD structure TFT 100 and the GOLD structure TFT 200. For example, the semiconductor device may include a plurality of LDD structure TFTs 100 as the pixel TFTs and a plurality of GOLD structure TFTs 200 as the driver circuit TFTs on the same substrate 1. In such a case, the semiconductor layers 3A, 3B can be formed by the same semiconductor film, and the gate electrodes 7A, 7B can be formed by the same electrically-conductive film. The gate insulating layer 5 and the interlayer insulating layer 11 may be common among the TFTs 100, 200. The source regions 33sA, 33sB and the drain regions 33dA, 33dB of the TFTs 100, 200 may be formed through a common contact doping step. In this case, the number of photomasks used in the manufacturing process of the semiconductor device can be reduced.

(25) Note that, in the semiconductor device of the present embodiment, it is only necessary that at least one high-concentration impurity region in a TFT which has an LDD region is formed through a contact doping step, and an electrode (source or drain electrode) is arranged so as to be in contact with that high-concentration impurity region inside the contact hole. Therefore, only either one of the source and drain regions may be formed through a contact doping step.

(26) In this specification, the LDD region refers to a region in which the impurity concentration is, for example, not less than 110.sup.18 atoms/cm.sup.3 and is lower than the impurity concentration of the source/drain regions. Therefore, a region of the semiconductor layer in which the impurity is contained at a very low concentration (less than 110.sup.18 atoms/cm.sup.3) is not included. For example, although there is a case where part of the impurity implanted into the LDD region diffuses into the channel region lying under the gate electrode, it is estimated that the impurity concentration in a portion in which the impurity is diffused is very low, and thus, such a portion is not included in the LDD region.

(27) Next, an example of a method for forming the LDD structure TFT 100 and the GOLD structure TFT 200 in the present embodiment is described step by step.

(28) FIGS. 3(a) to 3(d) are schematic stepwise cross-sectional views illustrating an example of a method for forming the LDD structure TFT 100.

(29) Firstly, as shown in FIG. 3(a), a semiconductor layer (e.g., polysilicon layer) 3A, a gate insulating layer 5 and a gate electrode 7A are formed in this order on the substrate 1 by a known method.

(30) Then, as shown in FIG. 3(b), an impurity ion of the first conductivity type (here, n-type) is implanted into the semiconductor layer 3A at a low concentration using the gate electrode 7A as a mask, whereby a low concentration implanted region 30A is formed in the semiconductor layer 3A. A region in which the impurity ion is not implanted is a channel region 31A. Thereafter, activation annealing is performed at the first temperature, whereby the impurity ion in the low concentration implanted region 30A is activated, and the crystallinity of the low concentration implanted region 30A is recovered.

(31) Then, as shown in FIG. 3(c), an interlayer insulating layer 11 is formed so as to cover the semiconductor layer 3A, and thereafter, a resist mask 41 which has openings is formed on the interlayer insulating layer 11. Then, a source contact hole 13A and a drain contact hole 14A are formed in the gate insulating layer 5 and the interlayer insulating layer 11 using the resist mask 41.

(32) Then, as shown in FIG. 3(d), an impurity ion of the first conductivity type is implanted into parts of the low concentration implanted region 30A at a high concentration via the source contact hole 13A and the drain contact hole 14A. Thereby, a source region 33sA and a drain region 33dA are formed in the semiconductor layer 3A. Part of the low concentration implanted region 30A in which the impurity ion is not implanted at the high concentration is the LDD region 32A. Thereafter, the resist mask 41 is peeled off. Note that peeling of the resist mask 41 may be carried out before implantation of the impurity ion.

(33) Then, activation annealing is performed at the second temperature, whereby the impurity ion implanted in the source region 33sA and the drain region 33dA is activated. The second temperature is set to, for example, a temperature lower than the first temperature. In this way, the LDD structure TFT 100 is obtained.

(34) FIGS. 4(a) to 4(d) are schematic stepwise cross-sectional views illustrating an example of a method for forming the TFT 200 that has a GOLD structure.

(35) Firstly, as shown in FIG. 4(a), a semiconductor layer 3B and a gate insulating layer 5 are formed on the substrate 1 by a known method. Then, a resist mask 42 is formed on the gate insulating layer 5. An impurity ion of the first conductivity type (here, n-type) is implanted into the semiconductor layer 3B at a low concentration using the resist mask 42, whereby a low concentration implanted region 30B is formed in the semiconductor layer 3B. A region in which the impurity ion is not implanted is the channel region 31B.

(36) After the resist mask 42 is peeled off, a gate electrode 7B is formed on the gate insulating layer 5 so as to extend over part of the low concentration implanted region 30B and the channel region 31B as shown in FIG. 4(b). Thereafter, activation annealing is performed at the first temperature, whereby the impurity ion implanted in the low concentration implanted region 30B is activated. Note that the activation annealing may be performed before formation of the gate electrode 7B.

(37) Then, in the same way as that previously described with reference to FIG. 3(c), an interlayer insulating layer 11 is formed, and the gate insulating layer 5 and the interlayer insulating layer 11 are patterned, whereby a source contact hole 13B and a drain contact hole 14B are obtained as shown in FIG. 4(c).

(38) Then, in the same way as that previously described with reference to FIG. 3(d), an impurity ion of the first conductivity type is implanted into parts of the low concentration implanted region 303 at a high concentration, whereby a source region 33sB and a drain region 33dB are obtained as shown in FIG. 4(d). Part of the low concentration implanted region 30B in which the impurity ion is not implanted at the high concentration is the LDD region 32B. Then, activation annealing is performed at the second temperature, which is lower than the first temperature, whereby a GOLD structure TFT 200 is obtained.

(39) According to the present embodiment, in formation of the LDD structure TFT 100, a low concentration implanted region (N.sup. region), which is to be the LDD region 32A, is formed using the gate electrode 7A as the mask, and a high concentration implanted region (N.sup.+ region), which is to be the source region or the drain region, is formed using the insulating layer which has the contact holes 13A, 14A as the mask. Also in the case of forming the GOLD structure TFT 200, a high concentration implanted region (N.sup.+ region) is formed using the insulating layer which has the contact holes 13B, 14B as the mask. Therefore, the number of photomasks used can be reduced by one as compared with the conventional method.

(40) In the above-described method, activation annealing is performed on the low concentration implanted region before contact doping. After the contact doping, activation annealing is performed on the high concentration implanted region. The activation annealing may be performed only once after the contact doping. Note that, however, as in the above-described method, it is preferred that the activation annealing is also performed before the contact doping. The reasons are as follows.

(41) Usually, a region in which an impurity ion is implanted is subjected to annealing (activation annealing) for restoring crystalline defects produced during the ion implantation and activating the implanted ion. However, if activation annealing is performed at a high temperature after the contact doping, terminal hydrogen at the interface between the gate insulating layer and the semiconductor layer separates from the contact hole, so that there is a probability that the TFT characteristics deteriorate. On the other hand, in the above-described method, after the low concentration implanted region (N.sup. region), which is to be the LDD regions 32A, 32B, has been formed, activation annealing is performed at the first temperature before the contact doping step, whereby the crystals of the low concentration implanted regions 30A, 30B are once restored. The first temperature may be, for example, not less than 500 C. and not more than 700 C. Then, after the contact doping, activation annealing is performed at the second temperature on the high concentration implanted region (N.sup.+ region). The second temperature can be set lower than the first temperature. The second temperature may be, for example, not less than 200 C. and less than 300 C. Thus, by performing the activation annealing before and after the contact doping, the crystallinity of the low-concentration impurity region and the crystallinity of the high-concentration impurity region can be more assuredly restored while the TFT characteristics are secured.

(42) The acceleration energy during the contact doping may be lower than the acceleration energy in formation of the low concentration implanted regions 30A, 30B and, for example, may be not less than 5 keV and not more than 30 keV. With such an acceleration energy, separation of the terminal hydrogen in the activation annealing which is performed after the contact doping can be effectively suppressed.

(43) Note that the conductivity type of the TFTs 100, 200 is not limited to the n-type but may be the p-type. In this case, the first conductivity type impurity implanted in the semiconductor layers 3A, 3B can be a p-type impurity, such as boron.

(44) Japanese Laid-Open Patent Publication No. 2007-141992 discloses forming source/drain regions by implanting an impurity ion into a semiconductor layer via a contact hole formed in a gate insulating layer. In this method, after formation of the source/drain regions, formation and patterning of an interlayer insulating layer are performed. According to this method, is necessary to separately pattern the gate insulating layer and the interlayer insulating layer, and the number of photomasks cannot be reduced. If the thickness of the gate insulating layer is small, the gate insulating layer cannot be used as the doping mask in some cases. On the other hand, in the present embodiment, the gate insulating layer 5 and the interlayer insulating layer 11, which are the gate insulating layers, are concurrently etched together, that the number of photomasks can be reduced. Since the gate insulating layer 5 and the interlayer insulating layer 11 are used as the etching mask, they are applicable irrespective of the thickness of the gate insulating layer 5. As previously described, performing the activation annealing twice separately before and after the contact doping is more advantageous.

Second Embodiment

(45) Hereinafter, a semiconductor device of the second embodiment of the present invention is described with reference to the drawings.

(46) The semiconductor device of the present embodiment includes an LDD structure TFT and a GOLD structure TFT on the same substrate. These TFTs are formed through a common process using the same semiconductor films. The LDD structure TFT is formed as the pixel TFT in the display region. The GOLD structure TFT is formed as the driver circuit TFT in the frame region.

(47) FIG. 5(a) is a cross-sectional view illustrating an LDD structure TFT 101 and a GOLD structure TFT 201 in a semiconductor device of the present embodiment. FIGS. 5(b) and 5(c) are plan views illustrating semiconductor layers 3A, 3B of the LDD structure TFT 101 and the GOLD structure TFT 201, respectively.

(48) In the LDD structure TFT 101, the LDD region 32A includes the third LDD regions (also referred to as high concentration LDD regions) 36 which are respectively in contact with the source region 33sA and the drain region 33dA and the fourth LDD regions (also referred to as low concentration LDD regions) 37 which are located between the third LDD regions 36 and the channel region 31A. The third LDD regions 36 contain an impurity of the first conductivity type at a higher concentration than in the fourth LDD regions 37. An this example, the fourth LDD regions 37 are in contact with the channel region 31A. In the illustrated example, when viewed in the normal direction of the substrate 1, the source region 33sA and the drain region 33dA are respectively provided inside the third LDD regions 36. The other components are the same as those of the LDD structure TFT 100 shown in FIG. 1, and therefore, the descriptions thereof are herein omitted.

(49) In the GOLD structure TFT 201, the LDD region 328 includes the first LDD regions (also referred to as high concentration LDD regions) 34 which are respectively in contact with the source region 33sB and the drain region 33dB and the second LDD regions (also referred to as low concentration LDD regions) 35 which are located between the first LDD regions 34 and the channel region 31B. The second LDD regions 35 are overlapped by the gate electrode 7B. When viewed in the normal direction of the substrate 1, the source region 33sB and the drain region 33dB are respectively provided inside the first LDD regions 34. The other components are the same as those of the GOLD structure TFT 200 shown in FIG. 1, and therefore, the descriptions thereof are herein omitted.

(50) Next, an example of the manufacturing method of the semiconductor device of the present embodiment is described.

(51) FIGS. 6(a) to 6(e) are schematic stepwise cross-sectional views illustrating a method for manufacturing the semiconductor device of the present embodiment. For the sake of simplicity, a method for forming a single unit of the LDD structure TFT 101 and a single unit of the GOLD structure TFT 201 is described herein although, typically, multiple units of the respective TFTs are formed.

(52) Firstly, as shown in FIG. 6(a), an island-like semiconductor layer 3A is formed in a region of the substrate 1 in which the LDD structure TFT is to be formed, and an island-like semiconductor layer 3B is formed in a region of the substrate in which the GOLD structure TFT is to be formed. Then, a gate insulating layer 5 is formed so as to cover these semiconductor layers 3A, 3B.

(53) The substrate 1 only needs to be a substrate which has an insulative surface. Not only a quartz substrate and a glass substrate but also a Si substrate and a metal substrate whose surface is covered with an insulating layer may be used.

(54) The semiconductor layers 3A, 3B are formed using a crystalline silicon film. Specifically, firstly, a semiconductor film which has an amorphous structure (here, amorphous silicon film) is deposited using a known method such as plasma CVD or sputtering. The thickness of the amorphous semiconductor film is not less than 20 nm and not more than 70 nm, preferably not less than 40 nm and not more than 60 nm. Thereafter, the amorphous semiconductor film is crystallized, whereby a crystalline semiconductor film (here, polysilicon film) is formed. The resultant crystalline semiconductor film is patterned, whereby semiconductor layers 3A, 3B are obtained. The crystallization of the amorphous semiconductor film can be realized by laser crystallization. Alternatively, the crystallization may be realized by adding a catalyst element to the amorphous semiconductor film and thereafter performing annealing on the amorphous semiconductor film.

(55) The gate insulating layer 5 can be formed by, for example, CVD. Here, a silicon oxide (SiO.sub.2) layer having a thickness of, for example, not less than 50 nm and not more than 200 nm is formed.

(56) Then, resist mask 45 covering part of the semiconductor layer 3A and a resist mask 47 covering part of the semiconductor layer 3B which is to be the channel region are formed through a known photolithography process. The resist mask 45 is arranged so as to expose part of the semiconductor layer 3A in which a high-concentration impurity region is to be formed and to cover parts of the semiconductor layer 3A in which the channel region and the LDD region are to be formed.

(57) Thereafter, a n-type impurity ion is implanted into the semiconductor layers 3A, 3B at a low concentration using the resist masks 45, 47, whereby low concentration implanted regions 50A, 50B are obtained (first ion implantation step). Here, phosphorus ion is implanted as the impurity ion. In the ion implantation, the acceleration voltage is for example 60 kV, and the dose amount is 110.sup.13/cm.sup.2. Part of the semiconductor layer 3B in which the impurity ion is not implanted is the channel region 31B.

(58) Then, the resist masks 45, 47 are removed, and gate electrodes 7A, 7B are formed on the semiconductor layers 3A, 3B, respectively, as shown in FIG. 6(b). The gate electrode 7A is provided on part of the low concentration implanted region 50A which is to be the channel region. The gate electrode 7B is provided so as to cover part of the low concentration implanted region 50B of the semiconductor layer 3B and the channel region 31B.

(59) The gate electrodes 7A, 7B can be realized by, for example, forming a tungsten (W) film (thickness: e.g., 400 nm) on the gate insulating layer 5 by sputtering and then etching the W film. The material of the gate electrodes 7A, 7B is not particularly limited. For example, the gate electrodes 7A, 7B may be a multilayer film including, for example, a TaN film and a W film.

(60) Then, as shown in FIG. 6(c), a n-type impurity ion is implanted into the semiconductor layers 3A, 3B at a low concentration using the gate electrodes 7A, 7B as the mask (second ion implantation step). Here, phosphorus ion is implanted as the impurity ion. In the ion implantation, the acceleration voltage is for example 50 kV, and the dose amount is 110.sup.13/cm.sup.2. Part of the semiconductor layer 3A which is covered with the gate electrode 7A and in which the impurity is not implanted is the channel region 31A, portion 36 in which the impurity ion is implanted at both the first and second ion implantation steps is the third LDD region. A portion 37 in which the impurity ion is not implanted at the first ion implantation step but the impurity ion is implanted at the second ion implantation step is the fourth LDD region. The third LDD region 36 contains the first conductivity type impurity at a concentration higher than the fourth LDD region 37.

(61) Thereafter, activation annealing (first activation annealing) is performed. The annealing temperature is not particularly limited but may be, for example, not less than 500 C. and not more than 700 C.

(62) Then, as shown in FIG. 6(d), an interlayer insulating layer 11 is formed so as to cover the semiconductor layers 3A, 3B, the gate electrodes 7A, 7B and the gate insulating layer 5. The interlayer insulating layer 11 may be, for example, a SiO.sub.2 film having a thickness of not less than 300 nm and not more than 900 nm. Alternatively, the interlayer insulating layer 11 may be a multilayer film consisting of, for example, a SiN film and a SiO.sub.2 film. Thereafter, when necessary, a heat treatment for hydrogenating the semiconductor layers 3A, 3B (hydrogenation annealing), for example, annealing at 350-550 C. in a 1 atm nitrogen atmosphere or hydrogen-mixed atmosphere, may be performed.

(63) Then, as shown in FIG. 6(e), a resist mask 49 is formed on the interlayer insulating layer 11, and the interlayer insulating layer 11 is patterned using the resist mask 49. As a result, the interlayer insulating layer 11 has a source contact hole 13A and a drain contact hole 14A, extending to part of the third LDD regions 36 of the semiconductor layer 3A, and a source contact hole 13B and a drain contact hole 14B, extending to part of the first LDD regions 34 of the semiconductor layer 3B.

(64) Then, via these contact holes 13A, 14A, 13B, 14B, an impurity ion is implanted into the semiconductor layers 3A, 3B (contact doping step). Thereby, source and drain regions 33sA, 33dA are formed in the third LDD regions 36 of the semiconductor layer 3A. Also, source and drain regions 33sB, 33dB are formed in the first LDD regions 34 of the semiconductor layer 3B. Thereafter, the resist mask 49 is removed. Note that the contact doping may be performed after the resist mask 49 is removed.

(65) The implantation conditions in the contact doping step are now described. Here, phosphorus ion is implanted as the impurity ion. In the ion implantation, the acceleration voltage is preferably set lower than the acceleration voltages of the first and second ion implantation steps, for example, set to a voltage lower than 20 kV. Since the ion implantation is performed on a region on which the ion implantation has already been performed twice, the dose amount in this step can be set to a value lower than the conventional dose amount in formation of the high concentration implanted region. Also, the dose amount in this step can be set lower than the dose amounts in the first and second ion implantation steps. Preferably, the dose amount is not less than 10.sup.13/cm.sup.2 and not more than 10.sup.14/cm.sup.2. As described herein, in the contact doping step, the ion implantation can be performed with a lower energy than in the first and second ion implantation steps, and accordingly, crystalline defects produced in the ion implantation can be reduced. Therefore, even if the temperature for the activation annealing performed after the ion implantation is decreased, the crystallinity can be sufficiently restored.

(66) Thereafter, the second activation annealing is performed, whereby the crystallinity of the source and drain regions 33sA, 33dA, 33sB, 33dB is restored, and the implanted ion is activated. Thereafter, although not shown, source electrodes and drain electrodes are formed in the contact holes 13A, 13B, 14A, 14B. In this way, the LDD structure TFT 101 and the GOLD structure TFT 201 are formed.

(67) The second activation annealing may be performed at a temperature lower than that of the above-described first activation annealing. The temperature of the second activation annealing may be set to, for example, a temperature lower than 300 C. In this case, separation of hydrogen from the contact holes 13A, 14A, 13B, 14B can be reduced, and accordingly, deterioration of the TFT characteristics can be suppressed.

(68) In the above-described method, the contact doping is utilized to form the high concentration implanted regions of the TFTs 101, 201, and therefore, it is not necessary to form a doping mask for formation of the high concentration implanted regions in a photo process. Thus, the number of photomasks used can be reduced as compared with the conventional method.

(69) In the present embodiment, the impurity concentration and the implantation profile in the fourth LDD region 37 of the LDD structure TFT 101 depend on the implantation conditions of the second ion implantation step. The impurity concentration and the implantation profile in the second LDD region 35 of the GOLD structure TFT 201 depend on the implantation conditions of the first ion implantation step. The first and third LDD regions 34, 36 are regions in which the impurity ion is implanted at both the first and second ion implantation steps. Therefore, the first and third LDD regions 34, 36 have substantially equal impurity concentrations and substantially equal implantation profiles. Also, the source and drain regions 33sA, 33dA, 33sB, 33dB, which are high-concentration impurity regions, have substantially equal impurity concentrations and substantially equal implantation profiles.

(70) Therefore, the following relationships hold:
c2<c1<c5(1)
c4<c3<c5(2)
c1=c3(3)
where c1, c2, c3, c4 are the impurity concentrations of the first to fourth LDD regions 34, 35, 36, 37, and c5 is the impurity concentration of the high-concentration impurity regions.

(71) In the foregoing, the method for forming the LDD structure TFT 101 and the GOLD structure TFT 201 which have two LDD regions of different impurity concentrations is described, although the LDD structure TFT 100 and GOLD structure 200 shown in FIG. 1 may be formed instead.

(72) Now, for the sake of comparison, a semiconductor device of a reference example which is manufactured without the contact doping is described. The semiconductor device of the reference example includes an LDD structure TFT 1000 and a GOLD structure TFT 2000 on the same substrate.

(73) FIG. 10(a) is a cross-sectional view illustrating the LDD structure TFT 1000 and the GOLD structure TFT 2000. FIGS. 10(b) and 10(c) are top views of semiconductor layers 3D, 3E of the LDD structure TFT 1000 and the GOLD structure TFT 2000, respectively. In FIG. 10, for the sake of simplicity, components equivalent to those of FIG. 1 to FIG. 5 are designated by the same reference marks.

(74) FIG. 7(a) is a process flow for the semiconductor device of the reference example which includes the LDD structure TFT 1000 and the GOLD structure TFT 2000. FIG. 7(b) is a process flow for the semiconductor device of the present embodiment which includes the LDD structure TFT 101 and the GOLD structure TFT 201. Note that FIGS. 7(a) and 7(b) are respectively the same as the process flows for the cases where only the GOLD structure TFT 2000 and the GOLD structure TFT 201 are formed.

(75) In the semiconductor device of the reference example, in order to separately form the high concentration implanted regions of the TFTs 1000, 2000 (the source regions 33sA, 33sB and the drain regions 33dA, 33dB) and the LDD region 32A of the LDD structure TFT 1000, a mask for formation of the high concentration implanted regions photo) is used. After the high concentration implanted regions have been formed, the contact holes 13A, 13B, 14A, 14B are formed which expose part of these regions, and source and drain electrodes 8A, 8B, 9A, 9B are formed inside the contact holes. Therefore, when viewed in the normal direction of the substrate 1, at the upper surface of the semiconductor layer, the edges of the source regions 33sA, 33sB and the drain regions 33dA, 33dB are not aligned with the edges of the contact holes 13A, 13B, 14A, 14B. On the other hand, in the present embodiment, the source regions 33sA, 33sB and the drain regions 33dA, 33dB are formed by the contact doping, and therefore, a mask for formation of the N.sup.+ region is unnecessary. Therefore, the number of photomasks can be reduced as compared with the semiconductor device of the reference example. As described herein, according to the present embodiment, the ADD structure TFT and the GOLD structure TFT can advantageously be formed on the same substrate without increasing the number of photomasks used.

(76) As seen from FIG. 7, according to the present embodiment, one photo step which is indispensable in the process flow of the reference example can be removed, i.e., one photomask can be removed. If the number of photomasks is decreased by one, the step of photolithographically forming a resist pattern (resist application, prebaking, exposure, development, post baking, etc.), the step of peeling off the resist pattern, and the washing and drying steps can be omitted, and accordingly, the number of steps of manufacture and the manufacturing cost can be reduced.

Third Embodiment

(77) Hereinafter, a semiconductor device of the third embodiment of the present invention is described with reference to the drawings. The semiconductor device of the present embodiment includes a first conductivity type TFT which has an LDD structure, a first conductivity type TFT which has a GOLD structure, and a second conductivity type TFT on the same substrate. In the present embodiment, the channel regions of the LDD structure and GOLD structure TFTs are provided with doping for adjustment of the threshold voltage (channel doping).

(78) In the following description, the first conductivity type is the n-type and the second conductivity type is the p-type, although the first conductivity type may be the p-type and the second conductivity type may be the n-type. The LDD structure TFT can be formed as the pixel TFT in the display region. The GOLD structure TFT and the p-type TFT are formed as the driver circuit TFTs in the frame region. The p-type TFT has, for example, a single drain structure.

(79) The semiconductor device of the present embodiment includes an n-type LDD structure TFT 102, an n-type GOLD structure TFT 202 and a p-type TFT 302 on the same substrate.

(80) The configurations of the LDD structure TFT 102 and the GOLD structure TFT 202 are the same as those of the LDD structure TFT 101 and the GOLD structure TFT 201, respectively, which have previously been described with reference to FIG. 5 except that an impurity is implanted in the channel regions 31A, 31B. Also, in these TFTs 102, 202, the arrangement of the LDD regions and the high-concentration impurity regions, the impurity concentration, the implantation profile, etc., are the same as those of the previously-described embodiments and, therefore, the description thereof is herein omitted.

(81) FIG. 8(a) is a cross-sectional view of the p-type TFT 302. FIG. 8(b) is a plan view of a semiconductor layer 3C of the p-type TFT 302. The p-type TFT 302 has, for example, a single drain structure. The p-type TFT 302 includes the semiconductor layer 3C formed on the substrate 1, a gate insulating layer 5 covering the semiconductor layer 3C, a gate electrode 7C formed on the gate insulating layer 5, an interlayer insulating layer 11 covering the gate electrode 7C and the semiconductor layer 3C, a source electrode 8C and a drain electrode 9C.

(82) The semiconductor layer 3C includes a channel region 31C, a source region 38s, a drain region. 38d, a source contact region 39s and a drain contact region 39d. The source region 38s is located between the source contact region 39s and the channel region 31C. Likewise, the drain region 38d is located between the drain contact region 39d and the channel region 31C. In this example, the source region 38s, the drain region 38d, the source contact region 39s and the drain contact region 39d are each a second conductivity type region (e.g., p.sup.+ type region) which contains the second conductivity type impurity (e.g., p-type impurity) at a high concentration.

(83) The source electrode 8C is in contact with the source contact region 39s of the semiconductor layer 3C inside a source contact hole formed in the gate insulating layer 5 and the interlayer insulating layer 11. The drain electrode 9C is in contact with the drain contact region 39d of the semiconductor layer 3C inside a drain contact hole formed in the gate insulating layer 5 and the interlayer insulating layer 11. At the upper surface of the semiconductor layer 3C, the edge of the source contact hole is aligned with the edge of the source contact region 39s. Likewise, the edge of the drain contact hole is aligned with the edge of the drain contact region 39d.

(84) In this example, the source contact region 39s and the drain contact region 39d are formed by contact doping. The concentration of the second conductivity type impurity in the source contact region 39s and the drain contact region 39d is equal to the concentration of the second conductivity type (e.g., p-type) impurity in the source region 38s and the drain region 38d. The concentration of the first conductivity type (e.g., n-type) impurity in the source contact region 39s and the drain contact region 39d is higher than the concentration of the first conductivity type impurity in the source region 38s and the drain region 38d by the amount of the impurity implanted by the contact doping.

(85) Next, an example of the manufacturing method of the semiconductor device of the present embodiment is described.

(86) FIGS. 9(a) to 9(f) are schematic stepwise cross-sectional views illustrating a method for manufacturing the semiconductor device of the present embodiment. For the sake of simplicity, a method for forming a single unit of the LDD structure TFT 102, a single unit of the GOLD structure TFT 202, and a single unit of the p-type TFT 302 is described herein although, typically, multiple units of the respective TFTs are formed.

(87) Firstly, as shown in FIG. 9(a), an island-like semiconductor layer 3A is formed in a region of the substrate 1 in which the LDD structure TFT is to be formed, an island-like semiconductor layer 33 is formed in a region of the substrate 1 in which the GOLD structure TFT is to be formed, and an island-like semiconductor layer 3C is formed in a region of the substrate 1 in which the p-type TFT is to be formed. Then, a gate insulating layer 5 is formed so as to cover these semiconductor layers 3A, 3B, 3C. The formation method of these layers are the same as that previously described with reference to FIG. 6(a).

(88) Then, a resist mask 45 covering part of the semiconductor layer 3A, a resist mask 47 covering part of the semiconductor layer 3B which is to be the channel region, and a resist mask 48 covering part of the semiconductor layer 3C which is to be the channel region are formed through a known photolithography process. The resist mask 45 is arranged so as to expose part of the semiconductor layer 3A in which a high-concentration impurity region is to be formed and to cover parts of the semiconductor layer 3A in which the channel region and the LDD region are to be formed. Here, a multilevel mask, such as halftone mask, is used as the resist mask 48.

(89) Thereafter, a n-type impurity ion is implanted into the semiconductor layers 3A, 3B, 3C at a low concentration using the resist masks 45, 47, 48, whereby low concentration implanted regions 50A, 50B, 50C are obtained (first ion implantation step). Here, phosphorus ion is implanted as the impurity ion. In the ion implantation, the acceleration voltage is for example 60 kV, and the dose amount is 110.sup.13/cm.sup.2.

(90) Then, as shown in FIG. 9(b), the resist masks 45, 47 are removed, and an ashing treatment (half ashing) is performed on the resist mask 48, whereby the height of the resist mask 48 is reduced. Thereafter, a p-type impurity is implanted into the semiconductor layers 3A, 3B, 3C using the height-reduced resist mask 48 as mask. The p-type impurity is implanted into a portion of the semiconductor layers 3A, 3B which is to be the channel region (channel doping). Here, for example, boron ion is implanted under the conditions that the acceleration voltage is 30 kV and the dose amount is 110.sup.12/cm.sup.2.

(91) Then, as shown in FIG. 9(c), gate electrodes 7A, 7B, 7C are formed on the semiconductor layers 3A, 3B, 3C, respectively. The gate electrode 7C is placed on part of the low concentration implanted region 50C of the semiconductor layer 3C which is to be the channel region. The formation method of the gate electrodes 7A, 7B, 7C and the arrangement of the gate electrodes 7A, 7B may be the same as those of the process which has previously been described with reference to FIG. 6(b).

(92) Then, a n-type impurity ion implanted into the semiconductor layers 3A, 3B, 3C at a low concentration using the gate electrodes 7A, 7B, 7C as the mask (second ion implantation step). The implantation conditions may be the same as the conditions for the second ion implantation step shown in FIG. 6(c). As a result, as previously described with reference to FIG. 6(c), the third and fourth LDD regions 36, 37 are formed in the semiconductor layer 3A, and the first and second LDD regions 34, 35 are formed in the semiconductor layer 3B.

(93) Then, as shown in FIG. 9(d), a resist mask 44 is provided so as to cover the LDD structure formation region and the GOLD structure formation region and expose the p-type TFT formation region, and a p-type impurity ion is implanted at a high concentration into the uncovered portion of the gate electrode 7C of the semiconductor layer 3C across the gate insulating layer 5. Thereby, a source region 38s and a drain region 38d are formed in the semiconductor layer 3C. For example, boron ion is implanted under the conditions that the acceleration voltage is not less than 50 kV and not more than 90 kV and the dose amount is not less than 510.sup.14/cm.sup.2 and not more than 510.sup.15/cm.sup.2, although the implantation conditions are not particularly limited.

(94) After the resist mask 44 is removed, activation annealing (first activation annealing) is performed. Thereby, the ion implanted in the semiconductor layers 3A, 3B, 3C by the first ion implantation step, the channel doping and the p-type impurity doping is activated, and the crystallinity of the semiconductor layers 3A, 3B, 3C is restored. The annealing temperature is not particularly limited but may be, for example, not less than 500 C. and not more than 700 C.

(95) Then, as shown in FIG. 9(e), an interlayer insulating layer 11 is formed so as to cover the semiconductor layers 3A, 3B, 3C, the gate electrodes 7A, 7B, 7C and the gate insulating layer 5. Thereafter, when necessary, hydrogenation may be performed. The formation method and the hydrogenation annealing method for the interlayer insulating layer 11 may be the same as those previously described with reference to FIG. 3(d).

(96) Then, as shown in FIG. 9(f), a resist mask 49 which has an opening is formed on the interlayer insulating layer 11, and the interlayer insulating layer 11 is patterned using the resist mask 49. Thereby, a source contact hole 13A and a drain contact hole 14A extending to part of the third LDD region 36 of the semiconductor layer 3A, a source contact hole 13B and a drain contact hole 14B extending to part of the first LDD region 34 of the semiconductor layer 3B, source contact hole 13C and a drain contact hole 14C extending to the source region 38s and the drain region 38d, respectively, of the semiconductor layer 3C are formed in the interlayer insulating layer 11.

(97) Then, via these contact holes 13A, 13B, 13C, 14A, 14B, 14C, impurity ion is implanted into the semiconductor layers 3A, 3B, 3C (contact doping step). The ion implantation conditions may be the same as the conditions for the contact doping step shown in FIG. 3(e). Thereby, source regions 33sA, 33sB and drain regions 33dA, 33dB are formed in the semiconductor layers 3A, 3B. In this step, the n-type impurity ion is also implanted into the semiconductor layer 3C that is to be the p-type TFT, whereby a source contact region 39s and a drain contact region 39d are obtained. Thereafter, the resist mask 49 is removed. Note that, in this contact doping step, a n-type impurity is implanted at a low dose into the source and drain regions 38s, 38d in which the p-type impurity has been implanted at a high concentration in the step shown in FIG. 9(d). Thus, the regions in which the n-type impurity is implanted (source contact region 39s, drain contact region 39d) would not change into n-type regions. Note that the contact doping may be performed after the resist mask 49 is removed.

(98) Thereafter, the second activation annealing is performed, whereby the crystallinity of the source/drain region of the semiconductor layers 3A, 3B and the contact regions 39s, 39d of the semiconductor layer 3C is restored, and the implanted ion is activated. Then, although not shown, a source electrode and a drain electrode are formed in respective TFTs. In this way, semiconductor device which includes the TFTs 102, 202, 302 is manufactured. The second activation annealing may be performed at a temperature lower than that of the above-described first activation annealing, for example, may be performed at a temperature lower than 300 C.

(99) In the above-described method, contact doping is utilized to form the high concentration implanted regions of the TFTs 102, 202. And, the halftone mask is utilized to perform channel doping. Therefore, it is not necessary to form the doping mask for formation of the high concentration implanted regions and the mask for the channel doping. Thus, the number of photomasks used can be reduced by two.

(100) Patent Document 1 and Japanese Laid-Open Patent Publication No. 2001-85695 disclose the methods for reducing the number of photomasks with the use of halftone mask. However, in these methods, it is necessary to control the line width of the resist pattern by etching. On the other hand, in the above-described method, a halftone mask is adopted for separate implantation in doping, and therefore, it is not necessary to control the line width. Thus, the number of photomasks can be reduced without deteriorating the line width controllability.

(101) Note that the method of the present embodiment not limited to the above-described method. The halftone mask for the channel doping may not be used. Alternatively, the channel doping may not be performed.

INDUSTRIAL APPLICABILITY

(102) The present invention is widely applicable to an oxide semiconductor TFT and a variety of semiconductor devices which include the oxide semiconductor TFT. For example, the present invention is also applicable to circuit boards such as active matrix substrates and the like, display devices such as liquid crystal display devices, organic electroluminescence (EL) display devices, inorganic electroluminescence display devices, MEMS display devices, and the like, imaging devices such as image sensor devices and the like, and various electronic devices such as image input devices, fingerprint readers, semiconductor memories and the like.

REFERENCE SIGNS LIST

(103) 1 substrate 3A, 3B, 3C semiconductor layer 5 gate insulating layer 7A, 7B, 7C gate electrode 8A, 8B, 8C source electrode 9A, 9B, 9C drain electrode 11 interlayer insulating layer 13A, 13B, 13C source contact hole 14A, 14B, 14C drain contact hole 30A, 30B low concentration implanted region 31A, 31B, 31C channel region 32A, 32B LDD region (low-concentration impurity region) 33sA, 33sB, 38s source region (high-concentration impurity region) 33dA, 33dB, 38d drain region (high-concentration impurity region) 34 first LDD region (high concentration LDD region) 35 second LDD region (low concentration LDD region, NM region) 36 third LDD region (high concentration LDD region) 37 fourth LDD region (low concentration LDD region) 39s source contact region 39d drain contact region 41, 42, 44, 45, 47, 49 resist mask 50A, 50B, 50C low concentration implanted region 200, 201, 202 GOLD structure TFT 100, 101, 102 LDD structure TFT