Laser assisted transfer welding process

Abstract

A method of printing transferable components includes pressing a stamp including at least one transferable semiconductor component thereon on a target substrate such that the at least one transferable component and a surface of the target substrate contact opposite surfaces of a conductive eutectic layer. During pressing of the stamp on the target substrate, the at least one transferable component is exposed to electromagnetic radiation that is directed through the transfer stamp to reflow the eutectic layer. The stamp is then separated from the target substrate to delaminate the at least one transferable component from the stamp and print the at least one transferable component onto the surface of the target substrate. Related systems and methods are also discussed.

Claims

1. A method of printing transferable components, the method comprising: providing a eutectic layer comprising a conductive material on a surface of a target substrate; providing a transfer stamp having front and back opposing sides and a plurality of protruding posts extending from the front side that uses kinetic or shear assisted control of adhesion to transfer arrays of semiconductor dies from a source wafer to a target substrate; providing two or more transferable semiconductor components on a source wafer, wherein the two or more transferable semiconductor components comprise two or more semiconductor dies; pressing two or more posts of the plurality of protruding posts against the two or more transferable semiconductor components on the source wafer to adhere the two or more transferable semiconductor components to the two or more posts of the transfer stamp, respectively; pressing the two or more posts with the two or more transferable semiconductor components against the eutectic layer on a side of the eutectic layer opposite the target substrate; during pressing of the two or more posts on the target substrate, exposing the two or more transferable semiconductor components to electromagnetic radiation directed through the two or more posts to reflow the eutectic layer; and then separating the two or more posts from the target substrate to delaminate the two or more transferable semiconductor components from the transfer stamp and print the two or more transferable semiconductor components onto the surface of the target substrate, wherein pressing the stamp includes applying external pressure to the back side of the stamp.

2. The method of claim 1, wherein the target substrate has a non-planar surface and the eutectic layer reflows to provide a substantially planar surface to which the transferable component is bonded.

3. The method of claim 1, wherein the target substrate is at least one of a non-planar substrate, an unpolished ceramic substrate, an unpolished polysilicon substrate, an unpolished metal substrate, a printed circuit board, and a plastic substrate.

4. The method of claim 1, wherein the eutectic layer is a self-planarizing layer.

5. The method of claim 1, wherein at least one of the opposite surfaces of the eutectic layer is non-planar.

6. The method of claim 1, wherein the transfer stamp includes a transparent portion that is at least partially aligned in plan view with the two or more transferable semiconductor components.

7. The method of claim 1, wherein the electromagnetic radiation is laser radiation.

8. The method of claim 1, the method further comprising selectively exposing some but not all of the two or more transferable semiconductor components to the electromagnetic radiation and delaminating from the transfer stamp only the exposed transferable semiconductor components.

9. The method of claim 1, wherein the eutectic layer is a multi-layer stack including at least two different layers.

10. The method of claim 1, wherein the eutectic layer has a first portion on the surface of the target substrate comprising a first eutectic stack and a second portion on the surface of the target substrate different from the first portion comprising a second eutectic stack different from the first eutectic stack, wherein the second portion is between respective ones of the two or more transferable semiconductor components and the target substrate, and wherein the first portion is adjacent to the second portion, and the first eutectic stack forms a bond between a semiconductor component and the target substrate.

11. The method of claim 10, further comprising selectively exposing to electromagnetic radiation the first eutectic stack to reflow the first eutectic stack without reflowing the second eutectic stack.

12. The method of claim 10, wherein the first eutectic stack has a higher melting temperature than the second eutectic stack.

13. The method of claim 10, wherein the first eutectic stack includes a metal alloy and the second eutectic stack includes a metal-semiconductor alloy.

14. The method of claim 1, further comprising identifying at least one of the two or more transferable semiconductor components as defective and other transferable semiconductor components as functional and selectively exposing the functional transferable semiconductor components of the two or more transferable semiconductor components to the electromagnetic radiation and delaminating from the stamp only the functional transferable semiconductor components.

15. The method of claim 1, wherein the eutectic layer provides an electrical connection between respective ones of the two or more transferable semiconductor components and a metal interconnection line on the target substrate.

16. The method of claim 1, wherein the two or more transferable semiconductor components comprise one or more metal fingers protruding from a surface thereof and the eutectic layer on the target substrate is in contact with the metal fingers during pressing of the transfer stamp on the target substrate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIGS. 1a-c present a schematic illustration of a transfer welding process according to some embodiments of the invention.

(2) FIGS. 2a-c present experimental results in accordance with some embodiments of the invention. The results validate effectiveness of embodiments of the invention in the case of semiconductor dies consisting of triple junction solar cells.

(3) FIG. 3 presents current-voltage characteristics of the bonded triple junction solar cell of FIGS. 2a-c under concentrated light.

(4) FIGS. 4a-b illustrate methods of transfer welding ultra-thin semiconductor dies onto rough target substrates when eutectic layers are reflowed under low compression forces according to some embodiments of the present invention.

(5) FIG. 5 illustrates a multilayer eutectic stack according to some embodiments of the present invention deposited and patterned on-top of a metal interconnect line to enable the formation of an electrical connection to the back side of a semiconductor die.

(6) FIGS. 6a-c present methods of transfer welding according to further embodiments of the present invention relying on the use of two eutectic stacks.

(7) FIGS. 7a-b present example embodiments of the invention enabling heterogeneous integration of high band-gap multi-junction solar cells onto low bandgap multi-junction solar cells, which can be grown onto separate source substrates.

(8) FIGS. 8a-b present example embodiments of the invention applied to a multi-terminal semiconductor die, which may contain an integrated circuit, optoelectronic, or power/high frequency device.

(9) FIGS. 9a-c present a double transfer process according to embodiments of the invention in which semiconductor dies are first transferred to a temporary carrier substrate.

(10) FIGS. 10 and 11 present schematic illustrations of a transfer process sequence according to embodiments of the invention, which can be used to interconnect an array of ultra-thin multi-terminal devices onto relatively large area rigid or plastic substrates.

(11) FIGS. 12a-b illustrate a transfer sequence of the invention permitting significant improvement of tool throughput on large area substrates through a reduction of the tool head travel distance.

DETAILED DESCRIPTIONS OF EMBODIMENTS

(12) The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. However, this invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout.

(13) It will be understood that when an element such as a component, layer, region or substrate is referred to as being on or extending onto or contacting another element, it can be directly on or extend directly onto or be in direct contact with the other element, or intervening elements may also be present. In contrast, when an element is referred to as being directly on or extending directly onto or directly contacting another element, there are no intervening elements present. It will also be understood that when an element is referred to as being in contact with or connected to or coupled to another element, it can be directly contacting or connected to or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being in direct contact with or directly connected to or directly coupled to another element, there are no intervening elements present.

(14) It will also be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention.

(15) Furthermore, relative terms, such as lower or bottom and upper or top, may be used herein to describe one element's relationship to another element as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in one of the figures is turned over, elements described as being on the lower side of other elements would then be oriented on upper sides of the other elements. The exemplary term lower, can therefore, encompasses both an orientation of lower and upper, depending of the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as below or beneath other elements would then be oriented above the other elements. The exemplary terms below or beneath can, therefore, encompass both an orientation of above and below.

(16) The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the description of the invention and the appended claims, the singular forms a, an and the are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term and/or as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms comprises and/or comprising, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

(17) Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. In other words, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.

(18) Unless otherwise defined, all terms used in disclosing embodiments of the invention, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs, and are not necessarily limited to the specific definitions known at the time of the present invention being described. Accordingly, these terms can include equivalent terms that are created after such time. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the present specification and in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. All publications, patent applications, patents, and other references mentioned herein are incorporated by reference in their entireties.

(19) Referring now to the drawings, FIGS. 1a-c present a schematic illustration of a transfer welding process in accordance with some embodiments of the invention. As used herein, the terms welding or transfer welding may generally refer to the joining of a transferable component with another component, layer, or substrate. In particular, in FIG. 1a, a transfer stamp 10 is used to selectively pickup an array of active transferable electronic components (illustrated as ultra-thin semiconductor dies 20) onto respective surfaces of raised post features 11 that protrude from a surface of the stamp 10. The transfer stamp 10 may be mounted to a transfer printing tool head, and a controller may be coupled to the transfer printing tool head to control one or more of the operations described herein. A single or multi-layer electrically conductive eutectic material (illustrated as eutectic stack 31) is deposited onto the surface of a destination substrate or target substrate 30. In FIG. 1b, the transfer stamp 10 is laminated onto the target substrate 30, bringing the array of semiconductor dies 20 into contact with the surface of the eutectic stack 31. Each semiconductor die 20 is temporarily heated using electromagnetic radiation provided by a light source (illustrated as a high power laser light beam 4), causing one or more of the eutectic layers 31 in physical contact with the semiconductor die to melt. As used herein, the electromagnetic radiation 4 is provided with a strength and duration that is sufficient to reflow the eutectic layer(s) 31, and includes electromagnetic radiation of any frequency, such as that provided by infrared lasers, ultraviolet lasers, etc., and thus is not limited to visible light. The stamp 10 (and one or more of the post features 11 protruding therefrom) may include one or more transparent layers or portions through with the laser light 4 may be transmitted. The transparent portion(s) of the stamp 10 may be aligned with the dies 20 in plan view. In this embodiment, each semiconductor die 20 itself is used as a lateral heat spreader. If the laser beam intensity profile is not perfectly uniform, laterally spreading the heat into the semiconductor die can be used as an effective way to improve the uniformity of the heat flux transferred to the eutectic layer(s) 31. In further embodiments, the wavelength of the laser can be selected to be longer than the semiconductor bandgaps. In such an embodiment, the semiconductor dies 20 are transparent to the laser beam 4, and thus the eutectic stack 31 can be directly heated by the laser beam 4.

(20) As shown in FIG. 1b, an external pressure can be applied to the back of the transfer stamp 10 (e.g., the surface of the stamp 10 opposite the surface from which the posts 11 protrude) during the course of the laser welding process. This external pressure is transferred by the stamp 10 to the semiconductor dies 20, which can improve the quality of the final bonded interface between the dies 20 and the eutectic layer 31 as the liquid eutectic layer stack 31 flows and wets the back surface of the semiconductor dies 20. In FIG. 1c, after the semiconductor dies 20 are bonded to the target substrate 30, the stamp 10 is moved away from the target substrate 30 to deposit or print the dies 20 onto the target substrate 30.

(21) FIGS. 2a-c present experimental results achieved according to some embodiments of the invention. The experimental results validated the effectiveness of some embodiments described herein in the case where the semiconductor dies include triple junction solar cells. In particular, a concentrator solar cell was laser transfer-welded onto the surface of an as fired (i.e. rough) ceramic substrate using an Indium-Gold based eutectic stack. A beam provided by a fiber coupled 808-nm solid state diode laser was precisely aligned and focused onto the surface of the triple junction solar cell to reflow the eutectic stack. The diameter of the laser beam spot was slightly smaller than the active area (650650 um) of the solar cell. In this configuration, the laser beam light was absorbed by the solar cell, which thus acted as a heat spreader to indirectly transfer heat and melt the Indium/Gold eutectic stack. The transfer stamp included a transparent silicone (polydimethylsiloxane (PDMS)) layer molded against a glass backing. The eutectic stack included a multilayer stack including four periods of alternating 100 nm-thick Indium and 5 nm-thick Gold layers. The layers of the eutectic stack were deposited by thermal evaporation with four repeats. The total thickness of the eutectic stack was thus approximately 420 nm. A 500 ms long laser pulse at a laser current bias of 7A was sufficient to successfully melt the eutectic layers and bond the solar cell to the ceramic substrate.

(22) FIGS. 2a and 2b respectively present high resolution optical images of a triple junction cell laser welded onto the surface of an unpolished ceramic substrate prior to (FIG. 2a) and after (FIG. 2b) removal of the solar cell photoresist layer encapsulation layer. FIG. 2c presents a high resolution near-infra red optical image of the bonded interface between the solar cell and the eutectic stack as captured using an InGaAs camera. This inspection camera is an effective method to visually inspect and assess the quality of the bonded interface. The micro-sized voids visible in this image are due to the high surface roughness of the as fired ceramic substrate. In this experiment, the total thickness of the eutectic layers (420 nm) was lower than the peak-to-valley roughness of this substrate (1,200 nm). The transfer welded solar cells pass a standard (Scotch) tape peel test, confirming the good mechanical strength of the bonded interface.

(23) FIG. 3 presents current-voltage characteristics of the bonded triple junction solar cell shown in FIGS. 2a-c under concentrated light. These electrical test results confirm that the laser welding process does not significantly adversely affect the performance of the transferred solar cell.

(24) FIGS. 4a-b schematically illustrate the use of electrically conductive eutectic layers for transfer welding according to embodiments of the present invention. In particular, as shown in FIG. 4a, a eutectic layer 31 is deposited on a rough surface of a target substrate 30 prior to contact with a semiconductor die 20. The eutectic layer 31 can be reflowed under low compression forces (<10 PSI) to provide a substantially planar surface to which the die 20 is bonded. More particularly, as shown in FIG. 4b, the melted eutectic layers planarize the rough surface of the target substrate and conform to the back surface of the semiconductor die 20.

(25) FIG. 5 schematically illustrates a multilayer eutectic stack 31 deposited and patterned on a metal interconnect line 33 to enable the formation of an electrical connection to the back side of a semiconductor die 20. The multilayer eutectic stack 31 includes capping layers 31, eutectic layers 31b-c, and diffusion barrier layers 31d. The composition and/or thickness of capping layers 31a, eutectic layers 31b-c, and diffusion barrier layers 31d can be selected and/or optimized to enable the formation of a low resistance ohmic metal-semiconductor contact upon reflow. In some embodiments, the laser welding process described herein can be performed under an inert or reducing gas environment to prevent oxidation.

(26) FIGS. 6a-c present a transfer welding process according to further embodiments that relies on the use of two eutectic stacks of differing composition. As shown in FIGS. 6a-c, a lower temperature first eutectic stack 31 is patterned or otherwise configured to bond to edge portions of the semiconductor die 20, and a higher temperature second eutectic stack 32 is patterned or otherwise configured to bond to the bottom surface of the semiconductor die 20. The first eutectic stack 31 may be formed of one or more eutectic layers which, after reflow, may be converted to an alloy having a higher melting temperature than a formation temperature of the second eutectic stack 32. For example, in some embodiments, the first eutectic stack 31 may include one or more metals and/or alloys thereof, while the second eutectic stack 32 may include semiconductors, metals, and/or alloys thereof. As such, a laser transfer welding process as described herein can be used to selectively reflow the first eutectic stack 31 without reflowing the second eutectic stack 32. In particular, a focused laser beam can be adjusted to selectively melt the first metal eutectic stack 31 at about the formation temperature of the first eutectic stack 31. After completion of the transfer welding process, the entire target substrate 30 can be uniformly heated inside a reflow oven at about the formation temperature of the second semiconductor-metal eutectic stack 32 to form an alloyed ohmic contact 32b at the bottom surface of the semiconductor die 20.

(27) In some embodiments, the composition of the metal eutectic 31 may be selected to have a formation temperature lower than the formation temperature of the semiconductor-metal eutectic 32, and the melting temperature of the formed metal eutectic alloy 31 may be higher than the formation temperature of the semiconductor-metal eutectic 32. For example, the first eutectic stack 31 may include InAu metal alloys, while the second eutectic stack 32 may include AuGe alloys, which are typically used to form ohmic contacts to GaAs semiconductor. In this specific case, the formation of InAu alloys of the first eutectic stack 31 can be initiated at temperatures as low as about 157 C., and the melting temperature of formed InAu alloys having indium weight percent composition in the 28 to 78% range (by weight) are higher than about 454 C. As the melting temperature of these InAu alloys is higher than the anneal temperature of the AuGe (356 C. eutectic) contacts provided by the second eutectic stack 32 on the GaAs semiconductor, the formed InAu alloys of the first eutectic stack 31 remain solid (e.g., are not reflowed) during a second reflow at temperatures in the range of about 360-450 C. (e.g., a temperature sufficient to reflow the second eutectic stack 32). This second reflow process can be performed under a vacuum to reduce the likelihood of trapping air pockets at the metal-semiconductor interface. The composition of the second metal eutectic 32 and/or doping of the semiconductor material can be selected and/or optimized to permit the formation of a low resistance ohmic electrical contact using standard practices.

(28) FIGS. 7a-b present embodiments of the invention that enable heterogeneous integration of high bandgap multi-junction solar cells (such as InGaP/GaAs 40) onto low bandgap multi-junction solar cells (such as InGaAsP/InGaAs 20), also referred to herein as a dual or tandem solar cell structure. The high bandgap and low bandgap multi-junction solar cells can be grown on separate source substrates. In this embodiment, a eutectic stack 22c and current collection metal grid fingers 22b can be deposited and patterned into cavities 23 etched into the low bandgap epitaxially grown semiconductor layers 20. In some embodiments, the lateral dimensions and spacing/positioning of the metal grid fingers are selected and/or optimized to reduce or minimize shadow losses when the cell structure is exposed to solar radiation. The total thickness of the grid metal and eutectic stack is selected and/or optimized to permit direct contact between the backside or lower surface of the high bandgap solar cell 40 and the top or upper surface of the low bandgap solar cell 20 after completion of the laser soldering process.

(29) In a subsequent step, the structure can be further annealed to initiate the formation of chemical bonds (such as hydrogen bonds) between the two solar cells 40 and 20. In such embodiments, a high optical quality (low shadow losses) and high thermal performance (direct semiconductor to semiconductor contact) interface between the solar cells 40 and 20 may be formed at low temperatures, which may allow for fabrication of ultra-high performance heterogeneously integrated multi-junction solar cells. Heterogeneous integration of InGaP/GaAs tandem solar cells 40 with InGaAsP/InGaAs tandem solar cells 20 can enable the fabrication of stacked solar cell structures capable of achieving greater than about 45% conversion efficiency under high optical concentration ratio.

(30) The typically poor electrical resistance (0.3 .Math.cm2) of wafer bonded stacked 4 J or 5 J solar cells structures reported, for example, in the article Directed semiconductor bonding technology (SBT) for high efficiency III-V multi-junction solar cells, Bhusari D. et al., IEEE PVSC 2011, may not permit efficient operation of such cells under high concentration ratios (i.e. >500 suns). In this article, the low and high bandgap solar cells were grown on separate substrates, thus reducing or eliminating lattice match growth constraints typically encountered in upfront monolithic growth approaches.

(31) In contrast to such wafer bonding processes, the herein disclosed eutectic bonded structure does not require the bonded semiconductor surfaces to be planarized down to the sub-nanometer level in order to achieve high bonding yield. The thickness, geometry, and/or depth of the metal grid fingers 22b, eutectic stack 22c, and etched cavities 23 can be selected and/or optimized to make the bonding process tolerant to surface roughness, which may be present on the top surface of the as-grown low bandgap solar cell 20. Unlike some other wafer bonding processes, the herein disclosed eutectic bonded structure does not require the top cell to be grown inverted.

(32) The herein disclosed dual or tandem 4 terminal solar cell structure can also offer additional performance advantages over wafer bonded structures, as the current generated by the top high bandgap cell 40 of the tandem cell can be independently extracted and thus does not have to be matched to the current generated by the bottom low bandgap cell 20 of the tandem cell. Such eutectic bonded structures may thus at least partially alleviate current matching constraints typically encountered in series connected monolithic solar cells.

(33) In the case of a InP-based low bandgap solar cell, the tandem cell can be released from a higher-cost InP growth substrate and transfer welded onto the surface of a lower-cost target substrate 30, in order to permit re-use of the higher-cost InP growth substrates. Such wafer re-use process has been demonstrated for the case of InGaP/GaAs tandem solar cells grown on GaAs substrates. In some embodiments, the low bandgap cell 20 can be transfer welded onto the surface of an electrically conducting metal layer 33 to enable the formation of a low resistance (ohmic) back-side contact.

(34) In order to provide electrical insulation between the bottom or lower contact 42a of the high bandgap cell 40 and the top or upper contact 22b of the low bandgap cell 20, an intrinsically doped layer or a P-N diode structure 41 can be incorporated at the bottom of the high bandgap 40 cell, that is, along the interface between the high bandgap 40 and low bandgap 20 cells. In such case, a highly doped lateral current spreading layer 42 can be incorporated at the bottom of the high bandgap solar cell epi design 40 (e.g., with the layer 41 between the current spreading layer 42 and the low bandgap cell 20) in order to reduce or minimize series resistance and thus permit high performance under high concentration ratios. To reduce or minimize shadow losses, the grid fingers 42b of the top high bandgap solar cell 20 can be designed to be precisely aligned (in plan view) with the metal grid fingers 22b of the bottom low bandgap solar cell 20. In addition, in order to further improve device performance, the herein disclosed integration approach can be used to heterogeneously integrate triple junction high bandgap solar cells (such as AlGaInP/InGaP/Ga(In)As) onto low bandgap tandem or triple junction low bandgap cells which can be grown on InP or GaSb substrates. The herein disclosed integration approach is also applicable to the heterogeneous integration of high bandgap solar cells onto non-lattice matched (i.e., metamorphic) solar cells, which may be grown on standard Ge or GaAs substrates.

(35) FIGS. 8a-b present examples of transfer welding processes in accordance with embodiments of the present invention applied to the case of a multi-terminal ultra-thin semiconductor die 20. The multi-terminal die 20 may include an integrated circuit, optoelectronic, or power/high frequency device. The die 20 may include one or more electrical elements (such as transistors, capacitors, resistors, and/or wires) and/or electro-optical elements (such as photo-sensors and/or light-emitting diodes), as well as electrical terminals 22 on a surface of the die 20 that may provide electrical connections to such elements. In such embodiments, the ultra-thin semiconductor die 20 can be presented upside down, i.e. with electrical terminals 22 facing down or opposite to the stamp. In these embodiments, the eutectic stack 31 is deposited and patterned on the surface of the terminals 22 of the semiconductor die 20, and the stamp including the die 20 on the post 11 protruding therefrom is moved toward the target substrate 30 such that the terminals 22 and the eutectic layer 31 thereon are brought into contact with conductive metal traces 33 on the target substrate 30. Upon exposure to electromagnetic radiation (for example, a focused laser beam), reflow of the eutectic stack 31 enables the formation of an array of electrical contacts between the semiconductor die 20 and conductive metal traces 33 defined on the surface of a target substrate 30. After completion of the laser welding process, the stamp is retracted and the transferred die 20 can be electrically tested without further processing.

(36) If defective dies are detected, these dies can be selectively removed from the array using a reversed sequence laser un-welding (rework) process. In particular, a single post of a stamp can be brought into contact with the defective die, the eutectic layer can be reflowed by exposure to electromagnetic radiation (for example, a high power laser pulse), and the stamp can be lifted to retrieve the defective die while the eutectic is melted. In a subsequent step, a new die can be re-soldered to replace the defective die. The composition of the metal eutectic stack can be selected or optimized to permit multiple rework processes to be performed at moderate reflow temperatures ranges. For example, AuSn based eutectics may be used over InAu eutectics as the re-melting temperature of the formed AuSn alloys remains below 400 C. for AuSn eutectic compositions having a gold weight percent fraction in the 70 to 82% range. Such a rework process may be used for applications, such as displays or digital X-ray detectors, requiring very large arrays (i.e., several thousands) of semiconductor dies to be interconnected onto backplanes with near 100% functional electrical yield. The rework capability of the herein disclosed transfer welding integration approach offers significant advantages over other metal over-edge interconnection processes, some of which may require more destructive (i.e., involving removal and re-deposition of dielectric and/or metal layers) rework procedures.

(37) FIGS. 9a-c present a double transfer process which enables semiconductor dies 20 fabricated using standard micro-fabrication processes to be first transferred to a temporary carrier substrate 50. In particular, as shown in FIG. 9a, the temporary carrier substrate 50 is brought into contact with a substrate 25 including the semiconductor dies 20 thereon. The substrate 25 may be a source substrate on which the semiconductor dies 20 were formed. The dies 20 may be anchored or otherwise attached to the substrate 25 by breakable tether structures 26. The breakable tether structures 26 may be electrically conductive in some embodiments. The pressure with which the stamp 10 is brought into contact with the substrate 25 is sufficient to break the tethers 26 anchoring the dies 20 to the substrate 25, and the dies 20 are thereby transferred to the temporary substrate 50 when the stamp 10 is retracted from the substrate 25, as shown in FIG. 9b.

(38) The temporary substrate 50 can be loaded onto a transfer printing tool in order to pick-up an array of dies 20 (front face/electrical terminals 22 facing down or toward the temporary substrate 50) using a transfer stamp 10, as shown in FIG. 9c. A low tack silicone adhesive layer 51 can be deposited onto the surface of the temporary carrier substrate 50 to facilitate the first transfer step (from the substrate 25 to the carrier substrate 50), and to permit high yield pickup during the second transfer step (from the carrier substrate 50 to the stamp 10). Additionally or alternatively, resistive thin film metal heater elements 53 may be patterned onto the surface of the temporary carrier substrate 50 prior to deposition of the low tack adhesive layer 51. These heater elements 53 may be powered during the second pick-up step of FIG. 9c to facilitate retrieval of the semiconductor dies 20 from the temporary carrier substrate 50. In particular, heat induced thermal expansion of the adhesive layer 51 can induce shear stresses, causing delamination at the interface between the semiconductor dies 20 and the adhesive layer 51.

(39) Transfer welding of micro-sized semiconductor dies also allows for integrating large array multi-terminal devices onto large area rigid or flexible substrates. Performing accurate layer to layer patterning steps on plastic substrates can be intrinsically challenging due to the typically poor dimensional stability of most plastic substrates when processed at moderate temperature. Embodiments of the present invention therefore provide an improvement over other methods for interconnecting ultra-thin multi-terminals devices onto large area substrates. For example, metal over-edge interconnection processes typically rely on the following process sequence: 1) in a first step, an array of multi-terminals devices are transfer printed (with terminals facing up) onto the surface of a target substrate; 2) in a second step, an interlayer dielectric is (optionally) deposited and patterned to open contact via areas over each device terminals; and 3) in a third step, a metal layer is deposited and patterned to form electrical interconnects. The alignment registration of patterning steps (2) and (3) can be limited by the dimensional stability of the target substrate, which may thus limit the maximum area which can be patterned in a single exposure step (for a chosen set of critical registration design rules). These and other limitations can be overcome with the transfer welding process according to embodiments described herein.

(40) FIGS. 10 and 11 present schematic illustrations of a process sequence which can be used to interconnect a relatively large array of ultra-thin multi-terminals devices onto relatively large area rigid or plastic substrates. In particular, as shown in FIG. 10, a metal layer is deposited and patterned over the surface of a target substrate 30 to define an array of interconnects 62 and local alignment marks 63. In FIG. 11, arrays of ultra-thin multi-terminals devices 20 are transfer welded onto the interconnect lines 62 defined on the surface of the target substrate 30. Locally defined alignment marks 63 are used to align each array of transferred devices. Accordingly, in the embodiments described herein, the alignment registration accuracy is not a function of the size of the target substrate 30, but mainly a function of the size of the transfer stamp 10 which is used during the transfer welding operation. The achievable alignment accuracy is thus affected by local deformations (within each stamped array), rather than by large area (global) deformation of the target substrate 30.

(41) The transfer welding integration approach according to embodiments described herein can also be used to improve transfer printing cycle throughput, which may be useful for applications requiring relatively large area target substrates. For example, multi-laser beams or fast scanning optics can be used to quickly transfer-weld a large array of dies in a time period which may be shorter than prior art transfer printing processes typically requiring slower (i.e. <1 mm/s) stamp delamination rates in order to achieve high transfer printing yield onto adhesive coated target substrates. In addition, as no adhesive is used on the target substrate, a continuous array of dies can be picked up from a source substrate and then selectively transfer welded onto the surface of a target substrate in successive print operations. In contrast with some conventional transfer printing processes, the transfer stamp does not necessarily need be repopulated with a new array of semiconductor dies after each selective print operation.

(42) FIGS. 12a-b illustrate an application of the transfer sequence in accordance with embodiments of the invention, which can permit significant improvement of tool throughput on large area substrates through a reduction of the tool head travel distance. In particular, as shown in FIG. 12a, a continuous array (i.e. non sparse) of semiconductor dies 20 are picked-up from a source wafer using a stamp 10, and the stamp 10 is pressed against a target substrate 30 such that the dies 20 are brought into contact with a eutectic stack 32 on the target substrate. A sparse array of the semiconductor dies 20 (e.g., a subset of the dies 20) are selectively laser welded onto the target substrate 30 by selectively exposing portions of the eutectic stack 32 to electromagnetic radiation (illustrated as a laser beam 4) to reflow the portions of the eutectic stack, thereby bonding the selected ones (but not all) of the semiconductor dies 20 thereto. As shown in FIG. 12b, the stamp 10 is then retracted and indexed over the target substrate 30 to a new print location. In subsequent transfer steps, additional sparse arrays of semiconductor dies can be selectively laser welded onto new print locations. Once the stamp 10 is fully depopulated (e.g., after multiple print operations), the transfer stamp 10 is realigned to the source substrate to pick up a new array of semiconductor dies 20.

(43) Accordingly, embodiments of the present invention as described herein provide an electrically conductive eutectic layer which can be selectively reflowed in response to electromagnetic radiation to bond printable semiconductor components to target substrates. As the eutectic layer solidifies (e.g., transitions from a liquid phase to a solid phase) more quickly than typical transfer printing delamination rates, embodiments of the present invention offer advantages in comparison to other transfer printing approaches, for example, in terms of throughput and accuracy.

(44) Although the invention has been described with reference to particular embodiments, it will be appreciated that variations and modifications may be made within the scope and spirit of the invention. Hence, it is intended that the above embodiments and all of such variations and modifications be included within the scope and spirit of the invention as defined by the claims that follow.