Method for manufacturing a grid

Abstract

A grid is manufactured with a combination of ion implant and epitaxy growth. The grid structure is made in a SiC semiconductor material with the steps of a) providing a substrate comprising a doped semiconductor SiC material, said substrate comprising a first layer (n1), b) by epitaxial growth adding at least one doped semiconductor SiC material to form separated second regions (p2) on the first layer (n1), if necessary with aid of removing parts of the added semiconductor material to form separated second regions (p2) on the first layer (n1), and c) by ion implantation at least once at a stage selected from the group consisting of directly after step a), and directly after step b); implanting ions in the first layer (n1) to form first regions (p1). It is possible to manufacture a grid with rounded corners as well as an upper part with a high doping level. It is possible to manufacture a component with efficient voltage blocking, high current conduction, low total resistance, high surge current capability, and fast switching.

Claims

1. A method for the manufacture of a grid structure in a silicon carbide (SiC) semiconductor material, the method comprising: providing a substrate comprising a doped semiconductor SiC material, the substrate comprising a first layer of a first conductivity type; epitaxial growth growing at least one doped semiconductor SiC material of a second conductivity type opposite to the first conductivity type on the first layer; removing parts of the epitaxial growth grown semiconductor SiC material to form separated second regions; and implanting ions in the first layer to form first regions of a second conductivity type opposite to the first conductivity type such that each of the separated second regions is in contact with one of the first regions, wherein the first regions have a lower doping concentration than the separated second regions.

2. The method of claim 1, wherein: the first regions have a first doping concentration in an interval of 1e18 cm3 to 1e19 cm3; and the separated second regions have a second doping concentration in an interval of 5e19 cm3 to 3e20 cm3.

3. The method of claim 1, further comprising: epitaxial growth growing a second layer on the separated second regions and on the first layer.

4. The method of claim 3, wherein the second layer is epitaxial growth grown such that a thickness of the second layer is in the interval 0.5 m to 3 m.

5. The method of claim 3, further comprising: performing a surface planarization of the second layer.

6. The method of claim 3, further comprising: making a Schottky contact on at least a part of the second layer.

7. The method of claim 1, further comprising: epitaxial growth growing a second layer on the first layer; and etching through portions of the second layer, wherein the separated second regions are formed within the etched portions.

8. The method of claim 1, wherein: a fraction of the first regions have a portion of the separated second regions on top; all of the first regions have a portion of the separated second regions on top; or a lower surface of the separated second regions in contact with the first regions is smaller than an upper surface of the first regions.

9. The method of claim 1, wherein the separated second regions have a thickness in an interval 0.1 m to 3.0 m.

10. The method of claim 1, wherein the epitaxial growth grown doped semiconductor SiC material has a doping gradient with a higher doping concentration furthest away from the first regions.

11. The method of claim 1, wherein the parts of the at least one doped semiconductor material are removed by dry etching.

12. The method of claim 1, wherein: the ion implantation is performed before forming the separated second regions; the method comprises simultaneously annealing the implanted ions in the first regions and epitaxial growth growing the at least one doped semiconductor SiC material on the first layer to form the separated second regions.

13. The method of claim 1, wherein: the first regions have a thickness in an interval 0.2 m to 2.0 m; or the first regions have a doping gradient with a higher doping concentration towards the second regions.

14. The method of claim 1, wherein: Al or B is utilized for doping of the first regions; Al is utilized for doping of the separated second regions and B is utilized for doping of the first regions; or B is utilized for doping of the first regions and the ion implantation is followed by diffusion.

15. The method of claim 1, further comprising: making an Ohmic contact directly on top of at least one of the separated second regions.

16. The method of claim 15, wherein making the Ohmic contact directly on top of the at least one of the separated second regions comprises removing at least a portion of a second layer to expose the at least one of the separated second regions.

17. The method of claim 1, wherein, for all spaces between any two of the separated second regions, a ratio between a thickness of the separated second regions to a spacing between the two separated second regions is below 1.

18. The method of claim 1, wherein an edge termination of a device is integrated into at least one of the first regions.

19. A grid structure in a semiconductor material manufactured according to the method of claim 1.

20. A device manufactured according to the method of claim 1.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The invention is described with reference to the following drawings in which:

(2) FIG. 1 shows a schematic cross-sectional view of a grid structure manufactured with the method according to the invention.

(3) FIG. 2 shows another schematic cross-sectional view of a buried grid structure manufactured with the method according to the invention.

DETAILED DESCRIPTION

(4) Before the invention is disclosed and described in detail, it is to be understood that this invention is not limited to particular compounds, configurations, method steps, substrates, and materials disclosed herein as such compounds, configurations, method steps, substrates, and materials may vary somewhat. It is also to be understood that the terminology employed herein is used for the purpose of describing particular embodiments only and is not intended to be limiting since the scope of the present invention is limited only by the appended claims and equivalents thereof.

(5) It must be noted that, as used in this specification and the appended claims, the singular forms a, an and the include plural referents unless the context clearly dictates otherwise.

(6) If nothing else is defined, any terms and scientific terminology used herein are intended to have the meanings commonly understood by those of skill in the art to which this invention pertains.

(7) Buried grid as used throughout the description and the claims denotes a grid structure of a material with one conductivity type in a material with the opposite conductivity type.

(8) Conductivity type as used throughout the description and the claims denotes the type of conduction in a semiconductor material. N-type denotes electron conduction meaning that excess electrons move in the semiconductor giving a current flow and p-type denotes hole conduction, meaning that excess holes move in the semiconductor giving a current flow. A n-type semiconductor material is achieved by donor doping and a p-type semiconductor by acceptor dopants. In SiC, nitrogen is commonly used as donor dopant and aluminum as acceptor dopant. If a material is a doped semiconductor such as SiC, the material either has conductivity type p or conductivity type n.

(9) A skilled person realizes that for most semiconductor devices comprising n-type and p-type doped materials, all doped materials can exchange conductivity type so that n becomes p and p becomes n. Thus also the versions where n is p-doped and p is n-doped are encompassed.

(10) Doped as used throughout the description and the claims denotes that an instrinsic semiconductor such as SiC has got added impurities to modulate its electrical properties and become an extrinsic semiconductor.

(11) Epitaxial as used throughout the description and the claims denotes that the material has been manufactured with epitaxial growth, in this case epitaxial growth of SiC.

(12) Substrate as used throughout the description and the claims denotes a piece of material on which the power device is built up.

(13) In a first aspect there is provided a method for the manufacture of a grid structure in a SiC semiconductor material, said method comprising the steps of: a) providing a substrate comprising a doped semiconductor SiC material, said substrate comprising a first layer n1, b) by epitaxial growth adding at least one doped semiconductor SiC material to form separated second regions p2 on the first layer n1, if necessary with aid of removing parts of the added semiconductor material to form separated second regions p2 on the first layer n1, c) by ion implantation at least once at a stage selected from the group consisting of directly after step a), and directly after step b); implanting ions in the first layer n1 to form first regions p1, wherein all of the second regions p2 are in contact with a first region p1.

(14) The first layer n1 is in one embodiment a lightly doped layer. There is a substrate comprising a first layer n1, and in one embodiment the substrate comprises one or more additional layer(s). Example of an additional layer includes but is not limited to a layer of opposite doping compared to the first layer n1.

(15) The ion implantation to form the first region p1 can be made before the second region p2 is formed on the first layer n1. However ions can also be implanted after the second region p2 is formed on top of the first layer n1. Then the ions are implanted through the second region p2 down into the first layer n1 below the second region p2 to form the first region p1.

(16) In the above embodiment the result is a surface grid. The invention can also be utilized for the manufacture of a buried grid. In one embodiment the method further comprises a step after step c) comprising epitaxial growth growing a second layer n2 on the second regions p2 and on the first layer n1. This will give a buried grid.

(17) There are several ways of manufacturing the grid according to the invention. In one embodiment the method further comprises a step directly after step a) comprising epitaxial growth growing a second layer n2 on the first layer n1 followed by etching through the entire second layer n2 on certain areas and wherein the subsequent step forms the separated second regions p2 on the bottom of the etched area. This also gives the same type of structures with second regions p2 on first regions p1.

(18) In one embodiment the first layer n1 and the second layer n2 are n-doped and the first region p1 and the second region p2 are p-doped.

(19) The grid structure is manufactured of SiC.

(20) When parts of the layer formed in step b) are removed the layer is completely removed on selected areas so that islands constituting the second regions p2 are formed. Thus the second regions p2 become separated.

(21) All of the second regions p2 are in contact with a first region p1, i.e. all second regions p2 have a first region p1 underneath but all first regions p1 do not necessarily have a second region p2 on top. In one embodiment all second regions p2 are aligned with a first region p1. This means that some of or all of the first regions p1 have a second region p2 on top and that such a second region p2 is aligned on a first region p1. The alignment means that the top surface of the first region p1 as seen from above matches the bottom surface of the second region p2 as seen from underneath. Top is defined as the direction in which the second region p2 is and bottom as the direction in which the first region p1 is.

(22) In one embodiment a fraction of the first regions p1 has a second region p2 on top. In some applications, only a part of the first regions p1 have a second region p2 on top. Thus a number of first regions p1 do not have a second region p2 on top whereby the second layer n2 is directly on the first region p1.

(23) In an alternative embodiment all first regions p1 have a second region p2 on top.

(24) In one embodiment the contact area between the first regions p1 and second regions p2 is such that the areas of the first region p1 and the second region p2 are matching and of equal size and of equal dimensions. In an alternative embodiment the surface of the second region p2 in contact with the first region p1 is slightly smaller than the area of the first region p1 to ensure that there is no corner of the highly doped p2 which may create undesired high electrical field.

(25) In one embodiment the epitaxial growth in step b) adds a layer with a thickness in the interval 0.1-3.0 m. This layer thickness defines the thickness of the second regions p2.

(26) In one embodiment the epitaxial growth in step b) utilizes Al as dopant.

(27) In one embodiment the epitaxial growth in step b) adds at least one layer with a doping concentration in the interval 5e19-3e20 cm.sup.3.

(28) In one embodiment the at least one layer added in step b) has a doping gradient with a higher doping concentration furthest away from the first region p1. The formed gradient of the second region p2 is an advantage when an Ohmic contact is to be formed directly on a second region p2.

(29) In one embodiment the removing of the second region p2 in step b) is performed by dry etching.

(30) In one embodiment the ion implantation is performed only before step b).

(31) In one embodiment the ion implantation in step c) is performed only before step b) and wherein the epitaxial growth in step b) is carried out at the same time as an annealing of the implanted first regions p1. Thereby the epitaxial growth and annealing of the implanted first regions p1 are carried out in one step which simplifies the production process.

(32) In one embodiment the ion implantation is performed with an energy of less than 350 keV. It should be kept in mind that high energy implantation is a costly process.

(33) In one embodiment the first region p1 has a thickness in the interval 0.2-2.0 m. The thickness of the first region p1 is determined by the ion implantation process. And to a minor extent also by subsequent annealing.

(34) In one embodiment the first region p1 has a doping concentration in the interval 1e18-1e19 cm.sup.3.

(35) In one embodiment the first region p1 has a doping gradient with a higher doping concentration towards p2. A gradient doping with the lowest doping level downwards towards n1 has the advantage of avoiding high electric fields at the pn-junction p1-n1. The higher doping level towards p2 gives a better emitter efficiency.

(36) In one embodiment B (boron) is utilized for doping of the first region p1 and wherein the ion implantation step is followed by a diffusion step. This will give a device with lower leakage current. In one embodiment B is implanted with higher energy compared to Al.

(37) In one embodiment at least one selected from the group consisting of Al and B is utilized for doping of the first region p1.

(38) In one embodiment Al is utilized for doping of the second region p2 and B is utilized for doping of the first region p1.

(39) In one embodiment, if the epitaxial growth of the second layer n2 is included in step b), it is carried out so that the thickness of the second layer n2 is in the interval 0.5-3 m.

(40) In one embodiment a surface planarization step is performed after growing of the second layer n2. In one embodiment CMP (chemical-mechanical planarization) is utilized for the planarization.

(41) In one embodiment an Ohmic contact is made directly on top of at least one of the second regions p2, if necessary by partial removal of the optional second layer n2 to expose p2. The part of the second layer n2 is removed above the region(s) p2 where the Ohmic contact is to be created. This will make p2 accessible for the creation of an Ohmic contact directly on p2. In one embodiment it is not necessary to remove a part of the second layer n2 to expose p2, then an Ohmic contact can be made directly on p2 without removal of a part of second layer n2.

(42) In one embodiment a Schottky contact is made on at least a part of the second layer (n2). For some embodiments a planarization may be required before deposition of a Schottky contact.

(43) In one embodiment the ratio between the thickness of p2 to the spacing between two second regions p2 is below 1. The ratio between the thickness of p2 to the spacing between two second regions p2 is below 1 for all spaces between any two second regions p2. The thickness of p2 is defined as the thickness of the layer grown in step b), assuming that no material is removed from the top of the second regions p2 during step c). The spacing is the distance between two second regions p2 measured at the n1-n2 interface. The spacing between two adjacent second regions p2 is the distance from one side of a second region p2 to the nearest side of the other second region p2. In many embodiments the pattern of second regions p2 is regular with equal spacing in all directions thereby making it easy to calculate the thickness to spacing ratio. For irregular patterns a ratio can be calculated for each space and then each ratio should be below 1.

(44) In one embodiment an edge termination of a device including the grid structure is integrated in the fabrication step c) to form the edge termination and first regions p1 at the same time.

(45) In a second aspect there is provided a grid structure in a semiconductor material manufactured with the method as described above. It is conceived that there is a plurality of first regions p1 and second regions p2 with spaces in between forming a grid structure. In various embodiments the first regions p1 and optionally with a second region p2 on top form patterns. One example is a hexagonal pattern seen from above. Other shapes are also encompassed.

(46) In a third aspect there is provided a device manufactured with the method as described above. The grid is then integrated in the device. One example of a device which can be made using a grid manufactured according to the method is a MOSFET. Further examples of devices which can be made using a grid manufactured according to the method include but are not limited to Schottky diodes, JFETs (Junction Field Effect Transistors), BJTs (bipolar junction transistors), and IGBTs (insulated-gate bipolar transistors).

(47) The grid is a feature in the device to be manufactured with regularly spaced oppositely doped regions. The exact design is determined by the component or device where the grid is to be used and its voltage, current, switching frequency etc.