PI-TYPE TRENCH GATE SILICON CARBIDE MOSFET DEVICE AND FABRICATION METHOD THEREOF

Abstract

The disclosure relates to a type trench gate silicon carbide MOSFET device and a fabrication method thereof. To protect a trench gate oxide layer without increasing a channel resistance and process complexity, a second conductivity type of heavily doped deep well inserted with double gate trenches along the sidewalls of deep well is designed. The deep well is connected to the source metal directly. The electric potential is clamped to the source during the voltage blocking and turn-off state, which reduces the electric field in the gate oxide and reduces the miller capacitance. An interlayer dielectric layer is deposited above the conductive dielectric polysilicon layers and extends outward separately to cover a part of the source region. A smaller cell pitch can be achieved by controlling the spacing between the first and the second trench gate, thereby increasing the channel density and reducing the channel resistance.

Claims

1. A type trench gate silicon carbide MOSFET device, comprising a drain electrode located at a bottom of the device and a source electrode located at a top of the device, a first conductivity type of heavily doped silicon carbide substrate being formed above the drain electrode, a first conductivity type of lightly doped epitaxial layer being formed on the first conductivity type of heavily doped silicon carbide substrate, and one or more second conductivity type of heavily doped deep well regions being arranged periodically on the first conductivity type of lightly doped epitaxial layer and the second conductivity type of heavily doped deep well regions being connected to the source electrode, a second conductivity type of well regions located between the second conductivity type of heavily doped deep well regions, and a first conductivity type of heavily doped source region and a second conductivity type of heavily doped contact region located above the second conductivity type of well regions, wherein a right sidewall and a left sidewall of the second conductivity type of heavily doped deep well regions are respectively provided with a first trench gate and a second trench gate that are shallower than the junction depth of the second conductivity type of heavily doped deep well region, the first trench gate and the second trench gate form a gate trench pair, the second conductivity type of well regions are formed on two sides of the gate trench pair, a distance between the first trench gate and the second trench gate is not larger than a width of a mesa between two adjacent gate trench pairs, a top of the first trench gate and a top of the second trench gate are each provided with an interlayer dielectric layer, the interlayer dielectric layer extends outward separately to cover a part of the first conductivity type of heavily doped source region, and the first trench gate and the second trench gate each comprise a gate dielectric layer and a conductive dielectric polysilicon layer filled in a trench, the source electrode is electrically connected with a part of the second conductivity type of heavily doped deep well region located between the first trench gate and the second trench gate in a gate trench pair.

2. The type trench gate silicon carbide MOSFET device according to claim 1, wherein a first conductivity type of current spreading layer is formed below the second conductivity type of well region, and a doping concentration of the first conductivity type of current spreading layer is higher than a doping concentration of the first conductivity type of lightly doped epitaxial layer and lower than a doping concentration of the second conductivity type of heavily doped deep well region.

3. The type trench gate silicon carbide MOSFET device according to claim 1, wherein the second conductivity type of heavily doped deep well regions are formed both below and between the first trench gate and the second trench gate.

4. The type trench gate silicon carbide MOSFET device according to claim 1, wherein a right sidewall of a first trench and a left sidewall of a second trench in the gate trench pair overlap with a side boundary of the second conductivity type of heavily doped deep well region.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0030] FIG. 1 shows a layout of a trench gate silicon carbide MOSFET device in the prior art and a schematic cross-sectional view of cells thereof along a line AB;

[0031] FIG. 2 shows a layout of a trench gate silicon carbide MOSFET device in the prior art and a schematic cross-sectional view of cells thereof along a line CD;

[0032] FIG. 3 is a schematic cross-sectional structural diagram of a trench gate silicon carbide MOSFET with tilted implantation on trench sidewalls in the prior art;

[0033] FIG. 4 is a schematic cross-sectional structural diagram of a type trench gate silicon carbide MOSFET device according to the first embodiment of the present disclosure;

[0034] FIGS. 5 to 12 are schematic cross-sectional views of main fabrication steps according to the first embodiment of the present disclosure;

[0035] FIG. 13 is a comparison of a channel resistance between a type trench gate silicon carbide MOSFET device according to the first embodiment of the present disclosure and a MOSFET with tilted implantation on trench sidewalls in the prior art;

[0036] FIG. 14 is a schematic cross-sectional structural diagram of a type trench gate silicon carbide MOSFET device according to the second embodiment of the present disclosure.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0037] It needs to be noted that the device structure herein is not limited to the metal oxide semiconductor field effect transistor (MOSFET), and other unipolar or bipolar device structures are also applicable. Likewise, the semiconductor material herein is not limited to the silicon carbide material, and other silicon, germanium, and gallium nitride materials are also applicable. The corresponding positional words such as up, down, left, and right described herein correspond to the relative positions with reference to the drawings, and are not limited to fixed directions in specific embodiments. The gate dielectric layer described herein is not limited to silicon dioxide and may be silicon nitride or hafnium dioxide layer. Likewise, the conductive dielectric material is not limited to doped polysilicon and may be other metal silicide film.

Embodiment 1

[0038] FIG. 4 is a schematic cross-sectional view of a type trench gate silicon carbide MOSFET device according to the first embodiment of the present disclosure. The device structure includes a drain electrode 301 at a bottom, a heavily doped silicon carbide N+ substrate 302 (including a buffer layer) on the drain electrode 301. A silicon carbide N-epitaxial layer 303 is located on the heavily doped silicon carbide N+ substrate 302 (including the buffer layer). On the surface of the epitaxial layer 303, there are first trench gate 304 and second trench gate 313. Gate trench pairs consist of the first trench gate 304, second trench gate 313 and a P+ deep well 307, which are arranged periodically. The distance between the first trench gate 304 and the second trench gate 313 is not larger than the width of mesa between two adjacent gate trench pairs. The trench gate includes a gate dielectric layer 305 and a conductive dielectric polysilicon layer 306. The right sidewall of the first trench gate 304 and the left sidewall of the second trench gate 313 are adjacent to the P type well region 308 and N-epitaxial layer 303. The bottom and left sidewall of the first trench gate 304 and the bottom and right sidewall of the second trench gate 313 locate in the P+ deep well 307. An N+ source region 309 is at the upper surface of P type well region 308 and adjacent to the gate trench. A P+ contact region 310 is at the upper surface of P type well region 308 and adjacent to the N+ source region 309. Interlayer dielectric layers 311 are located above the first trench gate 304 and the second trench gate 313, and cover a part of the N+ source region 309. A source metal 312 short-circuits the P+ contact regions 310, the N+ source regions 309, and the P+ deep well layers 307. The interlayer dielectric layers 311 isolate the source metal 312 from the gate electrode.

[0039] In addition, the present disclosure further provides a method for fabricating the device according to the first embodiment, as shown in FIGS. 5 to 12. Fabrication steps include: [0040] Firstly, an N-epitaxial layer 303 is grown on a heavily doped silicon carbide N+ substrate 302 (including a buffer layer), where a common doping impurity is nitrogen, as shown in FIG. 5; [0041] Secondly, a P+ deep well layer is formed on the upper surface of the N-epitaxial layer 303 by means of high-energy ion implantation, where a common implanted ion for the P+ deep well layer 307 is aluminum, and a common implantation temperature is 500 C., as shown in FIG. 6; [0042] Thirdly, a P well region, a P+ contact region, and a heavily doped N+ source region are implemented at the upper surface of the epitaxial layer by means of selective ion implantation. Then, high-temperature annealing is applied to activate the impurities, where a common annealing temperature is 1600-1800 C. Before the annealing process, a carbon cap needs to be sputtered to cover the surface of silicon carbide to prevent the out-diffusion of the impurities and migration of silicon carbide atoms on the surface, as shown in FIG. 7;

[0043] In this step, a first conductivity type of current spreading layer can be chosen to be added. It can be formed by selective ion implantation, wherein the doping concentration of the current spreading layer is higher than that of N-epitaxial layer 303 and lower than that of the second conductivity type of P+ deep well layer 307; [0044] Fourthly, a first trench and a second trench are formed in the P+ deep well region by means of dry etching, as shown in FIG. 8. The right sidewall of the first trench gate 304 and the left sidewall of the second trench gate 313 are adjacent to the P type well region 308 and N-epitaxial layer 303. The bottom and left sidewall of the first trench gate 304 and the bottom and right sidewall of the second trench gate 313 locate in the P+ deep well 307. [0045] Fifthly, a gate oxide layer is grown by means of dry oxidation followed by a post-oxide annealing process, as shown in FIG. 9; [0046] Sixthly, conductive dielectric of polysilicon layers are deposited followed by photolithography and etching, as shown in FIG. 10; [0047] Seventhly, interlayer dielectric layers are deposited. Then, photolithography and etching are done to pattern the interlayer dielectric, as shown in FIG. 11; [0048] Finally, an ohmic contact metal is sputtered on the front surface. The metal outside the contact hole is selectively removed followed by metal annealing. After that, a thick metal (such as aluminum), is sputtered and patterned by photolithography and etching. A passivation layer is formed on the front-side metal and pad is opened before the wafer thinning by grinding. Then, backside metal is sputtered and annealed, as shown in FIG. 12.

[0049] Compared with the prior art as shown in FIG. 3, the channel resistance of the present disclosure is reduced by 21% in the disclosure that the width of trench is 1 m and the spacing between trenches is 2.5 m (the prior art has the same size). The channel resistance can be further reduced if the cell pitch can be decreased.

Embodiment 2

[0050] FIG. 14 is a schematic cross-sectional structural diagram of a type trench gate silicon carbide MOSFET device according to a second embodiment of the present disclosure. Compared with the first embodiment of the present disclosure, the second embodiment has the following features: an N type current spreading layer 415 is designed below a P well region 408. The concentration of the N type current spreading layer 415 is higher than that of the N-epitaxial layer 403, but lower than that of the P+ deep well layer 407. The N type current spreading layer 415 is implemented to reduce the resistance formed between the lower boundary of a channel and the bottom of the P+ deep well layer 407.