A capacitor that includes an insulating substrate; a capacitance forming portion including a metal porous body, a dielectric film, and a conductive film; and a sealing portion that seals the capacitance forming portion. The capacitance forming portion is on a first main surface of the insulating substrate. A first external connection line including a first via conductor penetrating the insulating substrate from the first main surface side toward the second main surface side is connected to the metal porous body; and a second external connection line including a second via conductor penetrating the insulating substrate from the first main surface side toward the second main surface side is connected to the conductive film. When viewed in a normal direction of the first main surface, the first via conductor and the second via conductor are both in a region where the capacitance forming portion is disposed.

Disclosed herein is an electronic component that includes a substrate; and a plurality of conductive layers and a plurality of insulating layers which are alternately laminated on the substrate. The side surface of a predetermined one of the plurality of insulating layers has a recessed part set back from a side surface of the substrate and a projecting part projecting from the recessed part. The recessed part is covered with a first dielectric film made of an inorganic insulating material.

Disclosed herein is an electronic component that includes a substrate; and a plurality of conductive layers and a plurality of insulating layers which are alternately laminated on the substrate. The side surface of a predetermined one of the plurality of insulating layers has a recessed part set back from a side surface of the substrate and a projecting part projecting from the recessed part. The recessed part is covered with a first dielectric film made of an inorganic insulating material.

A method for manufacturing a capacitive device comprising the following steps: i) provide a substrate comprising: a first area made of a first material and/or having a first texture, a second area made of a second material and/or having a second texture, a third area made of a third material and/or having a third texture, ii) make nanopillars grow over the substrate with which a nanopillar layer is obtained locally having different densities, the density of the first area being lower than the density of the third area, iii) deposit an insulating layer, iv) deposit a conductive layer, with which a capacitive stack is formed at the first area, the capacitive stack comprising the insulating layer and the conductive layer.

A semiconductor device is provided having a semiconductor substrate with a circuit layer provided on a first main surface of the semiconductor substrate. The circuit layer includes a first and second electrode layers with a dielectric layer disposed therebetween, a first outer electrode electrically connected to the first electrode layer and a second outer electrode electrically connected to the second electrode layer. When the circuit layer is viewed from above, the first electrode layer has a first facing portion facing the second electrode layer in the thickness direction and a first non-facing portion not facing the second electrode layer, and the second electrode layer has a second facing portion facing the first electrode layer in the thickness direction and a second non-facing portion not facing the first electrode layer.

A semiconductor device is provided having a semiconductor substrate with a circuit layer provided on a first main surface of the semiconductor substrate. The circuit layer includes a first and second electrode layers with a dielectric layer disposed therebetween, a first outer electrode electrically connected to the first electrode layer and a second outer electrode electrically connected to the second electrode layer. When the circuit layer is viewed from above, the first electrode layer has a first facing portion facing the second electrode layer in the thickness direction and a first non-facing portion not facing the second electrode layer, and the second electrode layer has a second facing portion facing the first electrode layer in the thickness direction and a second non-facing portion not facing the first electrode layer.

A capacitor that includes an insulating substrate; a capacitance forming portion including a metal porous body, a dielectric film, and a conductive film; and a sealing portion that seals the capacitance forming portion. The capacitance forming portion is on a first main surface of the insulating substrate. A first external connection line including a first via conductor penetrating the insulating substrate from the first main surface side toward the second main surface side is connected to the metal porous body; and a second external connection line including a second via conductor penetrating the insulating substrate from the first main surface side toward the second main surface side is connected to the conductive film. When viewed in a normal direction of the first main surface, the first via conductor and the second via conductor are both in a region where the capacitance forming portion is disposed.

Embodiments described herein may be related to apparatuses, processes, and techniques related to stacked MIM capacitors with multiple metal and dielectric layers that include insulating spacers on edges of one or more of the multiple layers to prevent unintended electrical coupling between metal layers during manufacturing. The dielectric layers may include Perovskite-based materials. Other embodiments may be described and/or claimed.

Embodiments described herein may be related to apparatuses, processes, and techniques related to stacked MIM capacitors with multiple metal and dielectric layers that include insulating spacers on edges of one or more of the multiple layers to prevent unintended electrical coupling between metal layers during manufacturing. The dielectric layers may include Perovskite-based materials. Other embodiments may be described and/or claimed.

Embodiments described herein may be related to apparatuses, processes, and techniques related MIM capacitors that have a multiple trench structure to increase a charge density, where a dielectric of the MIM capacitor includes a perovskite-based material. In embodiments, a first electrically conductive layer may be coupled with a top metal layer of the MIM, and/or a second conductive layer may be coupled with a bottom metal layer of the MIM to reduce RC effects. Other embodiments may be described and/or claimed.