A multilayer electronic component includes a body including dielectric layers and internal electrodes alternately disposed in a first direction, and external electrodes disposed on the body to be connected to the internal electrodes. At least one internal electrode of the internal electrodes includes a plurality of disconnected portions penetrating through a respective internal electrode. A disconnected portion of the plurality of disconnected portions includes at least one of a pore or a dielectric substance disposed to connect adjacent dielectric layers to each other. A dielectric filling ratio, defined as a ratio of an overall length of the dielectric substance to an overall length of the disconnected portion on a cross section in the third and first directions, is more than 20% to 80% or less.

A multilayer electronic component includes a body including dielectric layers and internal electrodes alternately disposed in a first direction, and external electrodes disposed on the body to be connected to the internal electrodes. At least one internal electrode of the internal electrodes includes a plurality of disconnected portions penetrating through a respective internal electrode. A disconnected portion of the plurality of disconnected portions includes at least one of a pore or a dielectric substance disposed to connect adjacent dielectric layers to each other. A dielectric filling ratio, defined as a ratio of an overall length of the dielectric substance to an overall length of the disconnected portion on a cross section in the third and first directions, is more than 20% to 80% or less.

The present invention provides a method of fabrication and device made by preparing a photosensitive glass substrate comprising at least silica, lithium oxide, aluminum oxide, and cerium oxide, masking a design layout comprising one or more holes or post to form one or more high surface area capacitive device for monolithic system level integration on a glass substrate.

The present invention provides a method of fabrication and device made by preparing a photosensitive glass substrate comprising at least silica, lithium oxide, aluminum oxide, and cerium oxide, masking a design layout comprising one or more holes or post to form one or more high surface area capacitive device for monolithic system level integration on a glass substrate.

In a described example, an integrated circuit includes a capacitor first plate; a dielectric stack over the capacitor first plate comprising silicon nitride and silicon dioxide with a capacitance quadratic voltage coefficient less than 0.5 ppm/V.sup.2; and a capacitor second plate over the dielectric stack.

An improved process for preparing a conductive polymer dispersion is provided as is an improved method for making capacitors using the conductive polymer. The process includes providing a monomer solution and shearing the monomer solution with a rotor-stator mixing system comprising a perforated stator screen having perforations thereby forming droplets of said monomer. The droplets of monomer are then polymerized during shearing to form the conductive polymer dispersion.

Systems and methods are provided for presenting branding elements with electronic content. In one implementation, a method is provided that includes receiving, from a user device, a request that identifies a segment of electronic content and that contains information specifying a display configuration of the user device. The method further includes selecting first metadata including information defining how at least one branding element is to be presented based on the display configuration of the user device, and selecting second metadata for the requested segment of electronic content, the second metadata including information related to presenting the requested segment of electronic content. Additionally, the method includes instructing the user device to generate a presentation based on the selected first metadata and the selected second metadata, the presentation including the requested segment of electronic content and the at least one branding element.

Systems and methods are provided for presenting branding elements with electronic content. In one implementation, a method is provided that includes receiving, from a user device, a request that identifies a segment of electronic content and that contains information specifying a display configuration of the user device. The method further includes selecting first metadata including information defining how at least one branding element is to be presented based on the display configuration of the user device, and selecting second metadata for the requested segment of electronic content, the second metadata including information related to presenting the requested segment of electronic content. Additionally, the method includes instructing the user device to generate a presentation based on the selected first metadata and the selected second metadata, the presentation including the requested segment of electronic content and the at least one branding element.

A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.

A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.