A display device includes: a first semiconductor layer on a first buffer layer, and including a first active layer; a first gate insulating layer on the first semiconductor layer, and covering the first active layer; a first conductive layer on the first gate insulating layer, and including a first gate electrode; a second conductive layer on the first conductive layer, and including a first source/drain electrode; a first interlayer insulating layer on the first conductive layer; a second semiconductor layer on the first interlayer insulating layer, and including a second active layer; a second gate insulating layer on the second semiconductor layer, and covering the second active layer; and a third conductive layer on the second gate insulating layer, and including a second gate electrode and a second source/drain electrode. The first gate insulating layer and the second gate insulating layer include different insulating materials from each other.

In an electro-optical device, in an interlayer insulating layer provided in a layer between a transistor and a scanning line, a first opening and a second opening are respectively provided on both sides of a semiconductor layer in plan view, and a portion of a gate electrode is provided inside each of the first opening and the second opening. Therefore, the gate electrode configures a light shielding wall inside each of the first opening and the second opening. Of the first opening and the second opening, the first opening is provided at a position overlapping with the scanning line in plan view, and the gate electrode is electrically connected to the scanning line via the first opening. The second opening is provided at a position that does not overlap with the scanning line in plan view. Thus, the width of the scanning line can be made narrower.

A display device may include a substrate, a first active layer disposed on the substrate and including a first source region, a first drain region, and a first channel region disposed between the first source region and the first drain region, a first gate insulating layer covering the first active layer on the substrate, first gate electrodes disposed in opposite sides of the first channel region on the first gate insulating layer, a second gate insulating layer covering the first gate electrodes on the first gate insulating layer, a second gate electrode disposed in a central portion of the first channel region on the second gate insulating layer, and a first connection electrode disposed on the second gate electrode and connected to the first and second gate electrodes.

An array substrate includes a substrate, a first insulator layer on the substrate, a second insulator layer on the first insulator layer, a third insulator layer on the second insulator layer, and a first TFT and a second TFT on the substrate. The second TFT includes a second gate electrode on the first insulator layer, a second channel layer on the second insulator layer, and a second source electrode and a second drain electrode on the third insulator layer. The third insulator layer covers the second channel layer and defines a second source hole and a second drain hole.

Embodiments of the present disclosure provide an array substrate including a base substrate, an active layer on the base substrate, a first gate insulating layer on the active layer, a first gate on the first gate insulating layer, and a second gate insulating layer on the first gate. The second gate insulating layer includes a first sub-insulating layer and a second sub-insulating layer disposed in a direction away from the active layer, and a hydrogen content of the first sub-insulating layer is larger than a hydrogen content of the second sub-insulating layer. A method for fabricating the array substrate and a display panel including the array substrate are also provided.

The disclosure provides a bonding structure of a lateral side of a display panel, including an array substrate, a color filter, an inner circuit, and a lateral circuit. By defining a through hole in a gate insulating layer, a second metal layer may be directly connected to a first metal layer, thereby reducing layers flaked off from a glass when a lateral side of the glass is edged.

A thin film transistor includes a gate, a gate insulating layer, an active layer, an ionized amorphous silicon layer, a source and a drain. The gate insulating layer covers the gate. The active layer is disposed on a side of the gate insulating layer away from the gate. The ionized amorphous silicon layer is disposed on a side of the active layer away from the gate, and the ionized amorphous silicon layer is in contact with the gate insulating layer. The source and the drain are disposed on a side of the ionized amorphous silicon layer away from the gate insulating layer, and the source and the drain are coupled to the active layer through the ionized amorphous silicon layer.

The present disclosure relates to an insulation unit based on an array substrate and a manufacturing method thereof, an array substrate and a manufacturing method thereof, and a display mechanism. The method for manufacturing the insulation unit based on the array substrate includes: providing an aluminum layer on a substrate; and anodizing the aluminum layer to oxidize the aluminum layer to form the insulation unit. The method for manufacturing the insulation unit based on the array substrate can manufacture an insulation unit with a better corrosion resistance.

Provided are a display panel and a display device. The display panel includes a base substrate, a first transistor, and a second transistor. The first transistor and the second transistor are formed on the base substrate, the first transistor includes a first active layer, a first gate, a first source, and a first drain, and the first active layer comprises silicon; the second transistor includes a second active layer, a second gate, a second source, and a second drain, and the second active layer comprises an oxide semiconductor and is disposed on one side of the first active layer facing away from the base substrate. In a first direction perpendicular to the base substrate, a first distance between the first gate and the first active layer is D1, a second distance between the second gate and the second active layer is D2, and D1<D2.

A display device includes: a pixel at a display region. The pixel includes: a light-emitting element connected between a first power source and a second power source; and a first transistor connected between the first power source and the light-emitting element, the first transistor to control a driving current of the light-emitting element in response to a voltage of a first node. The first transistor includes a first driving transistor and a second driving transistor that are connected in series with each other between the first power source and the light-emitting element, and the first driving transistor and the second driving transistor have structures that are asymmetric with each other in a cross-sectional view.