Implementations of methods of forming capacitors may include depositing a first metal layer over a substrate, forming a photoresist layer over the first metal layer, patterning the photoresist layer, patterning the first metal layer using the pattern of the photoresist layer, depositing a dielectric layer over the first metal layer, and depositing a second metal layer over the dielectric layer to form a metal-insulator-metal capacitor.

A dielectric including a composite including a metal oxide having a rocksalt crystal structure and a beryllium oxide, and a capacitor, a transistor, and an electronic device including the same.

A capacitor is provided that includes a base having a first main surface and a second main surface opposing each other with a trench formed on a side of the first main surface (110A. Moreover, a dielectric film is disposed in a region that includes an inside of the trench on the side of the first main surface of the base; a conductor film is provided that includes a first conductor layer disposed on the dielectric film, which is the region including the inside of the trench and a second conductor layer disposed on the first conductor layer; and a stress relieving portion is provided in contact with at least a part of the end of the first conductor layer. Moreover, a thickness of the stress relieving portion is smaller than a thickness of the conductor film, outside the trench portion of the first main surface of the base.

MIM capacitors using low temperature sub-nanometer periodic stack dielectrics (SN-PSD) containing repeating units of alternating high dielectric constant materials sublayer and low leakage dielectric sublayer are provided. Every sublayer has thickness less than 1 nm (sub nanometer). The high dielectric constant materials could be one or more different materials. The low leakage dielectric materials could be one or more different materials. For the SN-PSD containing more than two different materials, those materials are deposited in sequence with the leakage current of the materials from the lowest to the highest and then back to the second-lowest, or with the energy band gap of the materials from the widest to the narrowest and then back to the second widest in each periodic cell. A layer of low leakage current dielectric materials is deposited on and/or under SN-PSD. The dielectric constant of SN-PSD is much larger than that of the component oxides and can be readily deposited at 250 C. using atomic layer deposition (ALD). The ALD deposition cycle could be 20-1000 cycles. The deposition technology is not limited to ALD, could be thermal oxidation, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD) and other thermal source assisted deposition.

In a described example, an integrated circuit includes a capacitor first plate; a dielectric stack over the capacitor first plate comprising silicon nitride and silicon dioxide with a capacitance quadratic voltage coefficient less than 0.5 ppm/V.sup.2; and a capacitor second plate over the dielectric stack.

The present invention provides a capacitor including a conductive porous base material with a porous part, a dielectric layer and an upper electrode. The porous part, the dielectric layer, and the upper electrode are stacked on top of one another in this order to define a capacitance formation part. The capacitance format ion part is not present at a lateral end part of the porous part.

A capacitor component includes: a semiconductor substrate including first and second portions, a trench penetrating through the substrate from one surface of the substrate to the other surface of the substrate to separate the first and second portions of the substrate from each other, a dielectric layer disposed in the trench and on the one surface of the substrate; a first pad electrode and a second pad electrode spaced apart from each other, and penetrating through the dielectric layer to be in contact with the first and second portions of the substrate, respectively, and a passivation layer disposed on the dielectric layer, covering portions of the first pad electrode and the second pad electrode, and exposing at least a portion of each of the first pad electrode and the second pad electrode.

A dielectric composition including a complex oxide containing bismuth, zinc, and niobium, includes a crystal phase formed of the complex oxide and having a pyrochlore type crystal structure, and an amorphous phase. When the complex oxide is represented by a composition formula Bi.sub.xZn.sub.yNb.sub.zO.sub.1.75+, in which x, y, and z satisfy relations of x+y+z=1.00, 0.20y0.50, and 2/3x/z3/2.

A capacitor includes: a semiconductor substrate; a first insulating layer disposed under the substrate; a first trench group disposed in the substrate and the first insulating layer, the first trench group includes two first trenches which penetrate through the substrate downward from an upper surface of the substrate and enter the first insulating layer, and bottoms of the two first trenches are communicated to form a first cavity structure located in the first insulating layer; a laminated structure disposed above the substrate, in the first trench group, and in the first cavity structure, the laminated structure includes m insulating layers and n conductive layers forming a structure that each insulating layer electrically isolates each conductive layer from each other; a first electrode layer electrically connected to all odd-numbered conductive layers; and a second electrode layer electrically connected to all even-numbered conductive layers.

An improved trench capacitor structure is disclosed that allows for the formation of narrower capacitors. An example capacitor structure includes a first conductive layer on the sidewalls of an opening through a thickness of a dielectric layer, a capacitor dielectric layer on the first conductive layer, a second conductive layer on the capacitor dielectric layer, and a conductive fill material on the second conductive layer. The capacitor dielectric layer laterally extends above the opening and along a top surface of the dielectric layer, and the conductive fill material fills a remaining portion of the opening.