A semiconductor-based capacitor can include a substrate including a semiconductor material, an oxide layer formed over the substrate, a conductive layer formed over at least a portion of the oxide layer, a plurality of distinct coplanar upper terminals, and a lower terminal. The upper terminals and the lower terminal can be exposed along the top and bottom surfaces of the substrate, respectively, for embedding the capacitor in a substrate such as a circuit board. The semiconductor-based capacitor can be sufficiently miniaturized to be embeddable within a circuit board while providing superior capacitance values without compromising the integrity of the capacitor. For example, each of the upper terminals can have a maximum width and a thickness normal to the maximum width, and a ratio of the width to the thickness can be greater than about 80:1 to prevent physical damage to the capacitor from warping or cracking.

Disclosed are devices having a metal-insulator-metal (MIM) capacitor and methods for fabricating the devices. The MIM capacitor includes a plurality of trenches in a Silicon (Si) substrate; a porous Si surface formed in the plurality of trenches, where the porous Si surface has an irregular surface on sidewalls and bottoms of the plurality of trenches; an oxide layer conformally disposed on the porous Si surface; a first plate conformally disposed on the oxide layer; a first dielectric layer conformally disposed on the first plate; and a second plate conformally disposed on the first dielectric, where the first plate, the first dielectric layer, and the second plate, each have an irregular surface that generally conforms to the irregular surface of the porous Si surface.

Ion booster for thrust generation. The invention pertains to electrical propulsion generated by the rapid acceleration of ions between asymmetrical electrodes. The invention is applicable for propulsion generation in atmospheric and space environments.

Provided are a capacitor and a method for manufacturing the capacitor, the capacitor including: a first thin-film electrode layer; a second thin-film electrode layer; a dielectric layer, including a binary metal oxide, between the first thin-film electrode layer and the second thin-film electrode layer; and an interlayer, including an anionized layer, between the dielectric layer and at least one of the first thin-film electrode layer or the second thin-film electrode layer. The interlayer has a same type of crystal structure as and a different composition from the dielectric layer, and the anionized layer includes at least one of a monovalent cation, a divalent cation, or a trivalent cation.

A stacked structure including: a single crystal substrate and, single crystal material on the single crystal substrate, wherein the single crystal material has a same crystallographic orientation as a crystallographic orientation of the single crystal substrate. Also a method of forming the stacked structure, a ceramic electronic component, and a device.

A MIM structure and manufacturing method thereof are provided. The MIM structure includes a substrate and a metallization structure over the substrate. The metallization structure includes a bottom electrode layer, a dielectric layer on the bottom electrode layer, a ferroelectric layer on the dielectric layer, a top electrode layer on the ferroelectric layer, a first contact electrically coupled to the top electrode layer, and a second contact penetrating the dielectric layer and the ferroelectric layer, electrically coupled to a base portion of the bottom electrode layer. The bottom electrode layer includes the base portion and a plurality of protrusions, each of the protrusions is protruding from the base portion and leveled with a lower surface of the dielectric layer, each portion of the dielectric layer over the bottom electrode layer substantially have identical thicknesses.

A multilayer ceramic electronic component includes: a body including a dielectric layer and a plurality of internal electrodes stacked on each other having the dielectric layer interposed therebetween; and an external electrode disposed externally on the body and connected to one or more of the internal electrodes. The body includes a first region in contact with the external electrode and a second region not in contact with the external electrode, and R.sub.1/R.sub.2 satisfies 3 to 15 in which R.sub.1 indicates a surface roughness R.sub.a of the first region and R.sub.2 indicates a surface roughness of the second region.

A method of manufacturing a semiconductor structure includes: forming a first oxide layer over a landing pad layer; forming a middle patterned dielectric layer over the first oxide layer; sequentially forming a second oxide layer and a top dielectric layer over the middle patterned dielectric layer; forming a trench through the top dielectric layer, the second oxide layer and the first oxide layer; conformally forming a bottom conductive layer in the trench; removing a portion of the top dielectric layer adjacent to the trench to expose a portion of the second oxide layer beneath the portion of the top dielectric layer; and performing an etching process to remove the second oxide layer and the first oxide layer from the portion of the second oxide layer. A semiconductor structure is also provided.

A semiconductor device includes a semiconductor substrate having first and second main surfaces that oppose each other in a thickness direction, and a circuit layer disposed on the first main surface. The circuit layer includes a first electrode layer on a side of the semiconductor substrate, a second electrode layer that faces the first electrode layer, a dielectric layer disposed between the electrode layers, and a first outer electrode electrically connected to the first electrode layer through an opening in the dielectric layer. An end portion of the dielectric layer on a side of the first region is in contact with the first electrode layer, and in the dielectric layer, a size of the end portion in the thickness direction is smaller than a size of an inter-electrode portion between the first and second electrode layers in the thickness direction.

An improved trench capacitor structure is disclosed that allows for the formation of narrower capacitors. An example capacitor structure includes a first conductive layer on the sidewalls of an opening through a thickness of a dielectric layer, a capacitor dielectric layer on the first conductive layer, a second conductive layer on the capacitor dielectric layer, and a conductive fill material on the second conductive layer. The capacitor dielectric layer laterally extends above the opening and along a top surface of the dielectric layer, and the conductive fill material fills a remaining portion of the opening.