Provided is a semiconductor package including: at least one first substrate including at least one first substrate terminal extended therefrom; at least one second substrate joined to the upper surface of the first substrate using ultrasonic welding; at least one semiconductor chip joined to the upper surface of the second substrate; a package housing covering the at least one semiconductor chip and an area of the second substrate, where ultrasonic welding is performed; and terminals separated from the first substrate, electrically connected to the at least one semiconductor chip through electric signals, and at least one of them is exposed to the outside of the package housing, wherein a thickness of the terminals formed inside the package housing is same as or smaller than a thickness of the first substrate and the second substrate includes at least one embossing groove on the upper surface thereof.

A semiconductor device is provided that includes a substrate, a pocket within the substrate, a solderable/glueable re-distribution layer arranged in the pocket and a die. The die is arranged downwards, so that a base contact and an emitter contact of the die face the bottom of the device, and a collector contact of the die faces the top of the device. The solderable/glueable re-distribution layer includes a first and second re-distribution layer part and the first re-distribution layer part and the second re-distribution layer part are isolated from each other by an isolating material. The emitter contact is connected to the first re-distribution layer part and the base contact is connected to the second re-distribution layer part. The emitter contacts via the first re-distribution layer part, the base contacts via the second re-distribution layer part, and the collector contact are fan out to the top surface of the semiconductor device.

Disclosed is a semiconductor package comprising a first semiconductor chip on a substrate, a second semiconductor chip between the substrate and the first semiconductor chip, and a spacer between the substrate and the first semiconductor chip. The substrate includes a first substrate pad between the second semiconductor chip and the spacer. The second semiconductor chip includes a chip pad and a signal wire. The spacer includes a first dummy pad on the spacer and a first dummy wire coupled to the first dummy pad. The first dummy pad is adjacent to the second semiconductor chip. The first semiconductor chip is attached to the second semiconductor chip and the spacer by an adhesive layer on the first semiconductor chip. A portion of each of the signal wire and the first dummy wire are in the adhesive layer.

A package structure includes a circuit element, a first semiconductor die, a second semiconductor die, a heat dissipating element, and an insulating encapsulation. The first semiconductor die and the second semiconductor die are located on the circuit element. The heat dissipating element connects to the first semiconductor die, and the first semiconductor die is between the circuit element and the heat dissipating element, where a sum of a first thickness of the first semiconductor die and a third thickness of the heat dissipating element is substantially equal to a second thickness of the second semiconductor die. The insulating encapsulation encapsulates the first semiconductor die, the second semiconductor die and the heat dissipating element, wherein a surface of the heat dissipating element is substantially leveled with the insulating encapsulation.

One or more embodiments are directed to semiconductor packages and methods in which one or more electrical components are positioned between a semiconductor die and a surface of a substrate. In one embodiment, a semiconductor package includes a substrate having a first surface. One or more electrical components are electrically coupled to electrical contacts on the first surface of the substrate. A semiconductor die is positioned on the one or more electrical components, and the semiconductor die has an active surface that faces away from the substrate. An adhesive layer is on the first surface of the substrate and on the one or more electrical components, and the semiconductor die is spaced apart from the one or more electrical components by the adhesive layer. Wire bonds are provided that electrically couples the active surface of the semiconductor die to the substrate.

An electronic component with a substrate connected a plurality of connection pins and on one face of which is affixed an electronic die fixing layer, and at least one electronic die assembled on said electronic die fixing layer. The electronic component includes a first heat exchanger and a layer of thermally conductive and electrically insulating material arranged in contact with said substrate. The first heat exchanger receives a circulating cryogenic fluid, and the electronic die, the electronic die fixing layer, the substrate, and the layer of thermally conductive and electrically insulating material as well as one end of each of said connection pins are enveloped in a volume of electrically insulating material at cryogenic temperature.

The present application discloses an underfill for chip packaging, including 19-25% of epoxy resin, 55-60% of filler, 15-25% of curing agent and 0.5-0.8% of accelerator in mass percentage, wherein the curing agent includes a polycondensate of paraxylene and dihydroxynaphthalene and a polycondensate of paraxylene and naphthol. Both of the polycondensate of paraxylene and dihydroxynaphthalene and the polycondensate of paraxylene and naphthol are selected to be used in the underfill for chip packaging in the present application, so that the underfill has stronger adhesiveness after being cured. In addition, the present application further provides a chip packaging structure using the underfill.

A packaging method and a package structure are provided. The packaging method includes the following steps. Firstly, a plurality of chips are disposed on a carrying surface of a carrying board for chip redistribution. Each of the chips includes a first side connected to the carrying surface and a second side opposite to the first side, and the second side is provided with at least one chip connecting member. Next, a base structure is provided. The base structure has a bonding surface provided with a plurality of predetermined areas for bonding the chips respectively, and each of the predetermined regions has at least one electrically connecting structure formed therein. Lastly, an encapsulating material is applied to integrate the base structure, the chips, and the carrying board into a unitary structure under specific hot pressing conditions.

Provided is a package structure includes a first die, a first dielectric layer, a second dielectric layer and a carrier. The first dielectric layer covers a bottom surface of the first die. The first dielectric layer includes a first edge portion and a first center portion in contact with the bottom surface of the first die. The second dielectric layer is disposed on the first dielectric layer and laterally surrounding the first die. The second dielectric layer includes a second edge portion and a second center portion. The second edge portion is located on the first edge portion, and the second edge portion is thinner than the second center portion. The carrier is bonded to the first dielectric layer through a bonding film.

An electrically conductive pillar that can bond a base member and a member to be bonded together with high bonding strength with a bonding layer interposed therebetween and a method for manufacturing the same. Specifically, an electrically conductive pillar 1 is composed of a sintered body 12 of metal micro-particles disposed on a base member 11. The average particle size of the metal micro-particles is less than 1 μm as measured using a small-angle X-ray scattering method. An upper surface 12b of the sintered body 12 has a concave shape recessed on the base member 11 side. The metal micro-particles are preferably made of one or more metals selected from Ag and Cu.