A dielectric ceramic composition having good characteristic even under high electric field intensity, and particularly good IR characteristic and high temperature accelerated lifetime. The present invention is a dielectric ceramic composition comprising, a main component comprising a perovskite type compound shown by a compositional formula (Ba1-x-ySrxCay)m(Ti1-zZrz)O3, a first sub component comprising oxides of a rare earth element, a second sub component as a sintering agent, wherein said dielectric ceramic composition is a complete solid solution particle wherein the rare earth element is solid dissolved to entire dielectric particle, or a core-shell particle having high ratio of the diffusion phase, and comprises the dielectric particle having 5 to 20 atom % of the average concentration of the rare earth element in the diffusion phase, and having uniform concentration distribution of the rare earth element in the diffusion phase.

A dielectric ceramic layer includes main phase grains and a secondary phase. The main phase grains include a perovskite-type compound. The perovskite-type compound includes Zr, Mn and at least one element selected from the group consisting of Ti, Ca, Sr, and Ba. In the perovskite-type compound, a molar ratio z between Ti/(Zr+Ti) satisfies 0≦z≦0.2, a molar ratio between Zr/(Zr+Ti) is equal to 1−z, a molar ratio x between Sr/(Ca+Sr+Ba) satisfies 0≦x≦1.0, a molar ratio y between Ba/(Ca+Sr+Ba) satisfies 0≦y≦0.3, a molar ratio between Ca/(Ca+Sr+Ba) is equal to 1−x−y, and a molar ratio m between (Ca+Sr+Ba)/(Zr+Ti) satisfies 0.95≦m<1.03. The secondary phase contains segregated Mn. In a body including the dielectric ceramic layer and an internal electrode alternately stacked, the secondary phase is located inside of a second region and not located inside of a third region.

A multilayer ceramic electronic component includes a ceramic body including a plurality of dielectric layers stacked on each other and having first and second surfaces opposing each other in a first direction, third and fourth surfaces opposing each other in a second direction, parallel to a stacking direction and connected to the first and second surfaces, and fifth and sixth surfaces opposing each other in a third direction and connected to the first to fourth surfaces, first and second external electrodes disposed on the first and second surfaces of the ceramic body, respectively, first and second conductive thin films disposed on at least one of the third and fourth surfaces, connected to the first and second external electrodes, respectively, and having a thickness lower than that of the first and second external electrodes, and first and second solder preventing films disposed on the first and second external electrodes, respectively.

A piezoelectric component includes a support substrate; a piezoelectric element having both ends fixed to the support substrate, so as to be oscillatable; a pair of terminal electrodes located below the ends of the piezoelectric element, respectively; a pair of capacitance-forming electrodes each having a greater width than the piezoelectric element, extending from the pair of terminal electrodes, respectively, toward a center of the piezoelectric element; and excitation electrodes disposed on a first principal surface and a second principal surface of the piezoelectric element, respectively, the excitation electrodes facing each other so that a facing region in which the excitation electrodes overlap with each other as seen in a transparent plan view is defined therebetween, at least part of a region of the pair of capacitance-forming electrodes which protrudes outside the facing region in a width direction thereof as seen in a plan view, being covered with an insulating film.

A multilayer ceramic capacitor includes a ceramic body including dielectric layers and first and second internal electrodes disposed to face each other with respective dielectric layers interposed therebetween; and first and second external electrodes disposed on outer surfaces of the ceramic body, wherein the dielectric layer contains zirconium (Zr), a Zr content is 2×Zr/(Ba+Ca+Ti+Zr) based on an atomic ratio, a first crystal grain is composed of a core part having a Zr content of 3.0 at % or less and a shell part having a Zr content of 4.0 to 15.0 at %, and a number fraction of the first crystal grain to all crystal grains in the dielectric layer is 4% or more.

In an electronic component, a first outer electrode includes a first conductive layer provided on a first end surface. A second outer electrode includes a second conductive layer provided on a second end surface. A first inner electrode passes through the first conductive layer. A second inner electrode passes through the second conductive layer.

Provided is a manufacturing method of a thin film capacitor comprising a capacitance portion in which at least one dielectric layer is sandwiched between a pair of electrode layers included in a plurality of electrode layers, the manufacturing method including a lamination process of alternately laminating the plurality of electrode layers and a dielectric film and forming a laminated body which will be the capacitance portion, a first etching process of forming an opening extending in a laminating direction with respect to the laminated body and exposing the dielectric film laminated directly on one of the plurality of electrode layers on a bottom surface of the opening, and a second etching process of exposing the one electrode layer at the bottom surface of the opening. In the second etching process, an etching rate of the one electrode layer is lower than an etching rate of the dielectric film.

A thin film laminate structure, an integrated device including the same, and a method of manufacturing the thin film laminate structure are provided. The thin film laminate structure includes two or more dielectric layers, wherein at least one of the dielectric layers of the thin film laminate structure includes a compound represented by Formula 1 and having a perovskite-type crystal structure having a B/B′ composition ratio different from that of a remainder of the dielectric layers:

AB.sub.1-xB′.sub.xO.sub.3  <Formula 1> wherein, in Formula 1, A, B, B′, and x are the same as defined in the specification.

A module having a power semiconductor device and a ceramic capacitor which is configured for cooling the power semiconductor device.

A multilayer ceramic capacitor includes a ceramic body having a dielectric layer disposed between two internal electrodes. The dielectric layer includes a plurality of dielectric grains. A grain boundary between at least two dielectric grains of the plurality of dielectric grains has a ratio Si/Ni of a weight of Si to a weight of Ni in the grain boundary that is at least 1 and 6 or less.