A 3D semiconductor device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where a second metal layer is disposed atop the first metal layer; a plurality of logic gates including the first metal layer and first transistors; a plurality of second transistors disposed atop the second metal layer; a plurality of third transistors disposed atop the second transistors; a top metal layer disposed atop the third transistors; and a memory array including word-lines, where the memory array includes at least four memory mini arrays, where each of the mini arrays includes at least two rows by two columns of memory cells, where each memory cell includes one of the second transistors or one of the third transistors, and where one of the second transistors is self-aligned to one of the third transistors, being processed following a same lithography step.

A 3D semiconductor device, the device including: a first level including a first single crystal layer and first single crystal transistors; a first metal layer; a second metal layer disposed atop the first metal layer; second transistors disposed atop of the second metal layer; third transistors disposed atop of the second transistors, where at least one of the third transistors includes at least one replacement gate, being processed to replace a non-metal gate material with a metal based gate, and where a distance from at least one of the third transistors to at least one of the first transistors is less than 2 microns.

A thin film transistor, an array substrate, a display panel and a display device are provided, which is related to the field of display technologies. A thin film transistor comprises: a substrate; at least two active layers on the substrate, each active layer comprising a first terminal and a second terminal opposite to each other; a source and a drain above the substrate. The first terminal of each of the at least two active layers is electrically connected to the source, and the second terminal of each of the at least two active layers is electrically connected to the drain, and the at least two active layers are arranged on an upper surface of the substrate and separated from one another.

A display device including a substrate, a first gate electrode, a second gate electrode, an active layer, and a first data electrode is provided. The active layer is disposed between the first gate electrode and the second gate electrode. And one of the first gate electrode and the second gate electrode is connected to the data line, so as to reduce the off leak current.

The disclosure relates to a display device, including a first substrate, a light emitting component, an insulating layer, and a conductive element. The first substrate has a driving component and a common line. The light emitting component is disposed on the first substrate and has a first electrode and a second electrode. The first electrode is electrically connected to the driving component. The insulating layer is disposed to the first substrate and has a first opening and a second opening. The first opening exposes the second electrode of the light emitting component. The second opening exposes the common line. The common line is electrically connected to the second electrode through the conductive element.

Embodiments herein describe techniques for a semiconductor device including a capacitor and a transistor above the capacitor. A contact electrode may be shared between the capacitor and the transistor. The capacitor includes a first plate above a substrate, and the shared contact electrode above the first plate and separated from the first plate by a capacitor dielectric layer, where the shared contact electrode acts as a second plate for the capacitor. The transistor includes a gate electrode above the substrate and above the capacitor; a channel layer separated from the gate electrode by a gate dielectric layer, and in contact with the shared contact electrode; and a source electrode above the channel layer, separated from the gate electrode by the gate dielectric layer, and in contact with the channel layer. The shared contact electrode acts as a drain electrode of the transistor. Other embodiments may be described and/or claimed.

A semiconductor device includes a stack of layers stacked vertically and including a source layer, a drain layer and a channel layer between the source layer and the drain layer. A gate electrode is formed in a common plane with the channel layer and a gate dielectric is formed vertically between the gate electrode and the channel layer. A first contact contacts the stack of layers on a first side of the stack of layers, and a second contact formed on an opposite side vertically from the first contact.

A thin-film transistor, method of manufacturing the same, and a display apparatus are provided. The thin-film transistor includes a first active layer, a source, a drain, a gate, and a second active layer, the source, the drain, the gate are disposed on the first active layer with spacing, the gate is located between the source and the drain, the second active layer is disposed on the gate, the source, and the drain, the source and the drain are both respectively connected to the first active layer and the second active layer, and the gate is respectively insulated from the first active layer, the second active layer, the source, and the drain. When a voltage is applied to the gate, the source and the drain may be conducting via the first and second active layer. Therefore, a larger current may flow between the source and the drain.

A TFT, OLED display including the same, and manufacturing method thereof are disclosed. In one aspect, the TFT includes a first gate electrode formed over a substrate and a first insulating layer formed over the substrate and the first gate electrode. A semiconductor layer is formed over the first insulating layer, the semiconductor layer at least partially overlapping the first gate electrode. A second insulating layer is formed over the first insulating layer and the semiconductor layer, the first and second insulating layers having a pair of connection holes formed therethrough. A second gate electrode is electrically connected to the first gate electrode via the connection holes, the connection holes respectively exposing portions of the first gate electrode. Source and drain electrodes are formed over a third insulating layer and electrically connected to the semiconductor layer via the contact holes, the contact holes respectively exposing portions of the semiconductor layer.

A transistor having a vertical structure can include a substrate, a first electrode disposed on the substrate, a second electrode disposed on the substrate, an insulation pattern disposed between the first electrode and the second electrode, an active layer connected between the first electrode and the second electrode, a channel area of the active layer disposed along a side surface of the insulation pattern and around an upper edge of the insulation pattern, a gate electrode disposed on the active layer, and a gate insulating film disposed between the gate electrode and the active layer.