A display device with high resolution is provided. A display device with high display quality is provided. A display device includes a display portion, a first terminal group, and a second terminal group. The display portion includes pixels, scan lines, and signal lines. The first terminal group and the second terminal group are apart from each other. The first terminal group includes first terminals and the second terminal group includes second terminals. The scan lines are each electrically connected to the pixels arranged in a row direction. The signal lines are each electrically connected to the pixels arranged in a column direction. The signal lines are each electrically connected to the first terminal or the second terminal. The display portion includes a first region where the signal lines electrically connected to the first terminals and the signal lines electrically connected to the second terminals are mixed.

A method for producing a 3D memory device, the method including: providing a first level including a first single crystal layer; forming a plurality of first transistors each including a single crystal channel; forming a first metal layer and a second metal layer, where the first level includes the plurality of first transistors, the first metal layer, and the second metal layer; forming at least one second level disposed above the second metal layer; performing a first etch step including etching first holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching second holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level, where memory cells each include one memory transistor.

A pixel driving circuit and a display panel are provided. The pixel driving circuit includes a source of a second thin film transistor electrically connected to a drain of a first thin film transistor, a gate of a sixth thin film transistor configured to receive a third control signal, a source of the sixth thin film transistor electrically connected to a second node, and a drain of the sixth thin film transistor electrically connected to an anode of a light emitting device.

A body layer formed of a semiconductor layer, the body layer comprising, a first region, a second region, and a channel region positioned therebetween; a channel stopper formed on the channel region; source and drain electrodes electrically connected to the first and second regions via first and second contact layers respectively are provided. Each of the first and second contact layers comprises an impurities-containing first amorphous silicon layer; a thickness of each of the first and second regions is less than a thickness of the channel region; and the first and second regions comprise a second amorphous silicon layer containing impurities in a concentration being less than a concentration of impurities contained in the first amorphous silicon layer. This makes it possible to suppress a photoexcited current and improve the aperture ratio in a case that a display apparatus is configured.

A thin film transistor (TFT) and a method of manufacturing same are provided. A photoresist layer is dry-etched to form a tunnel before an active layer is formed, wherein a bottom of the tunnel is a copper trace layer. After that, two edges of the photoresist layer are aligned with two edges of the copper trace layer. Therefore, the photoresist layer won't protrude over an amorphous silicon layer to block the etching gas from etching the amorphous silicon layer. As a result, an aperture ratio of the TFT is increased, and quality of the TFT is improved. By forming an oxidation protective layer on the tunnel, the copper trace layer is prevented from being reacted with the etching gas to form a compound. Therefore, metals or compounds on the tunnel can be completely etched, and quality of the TFT is further improved.

The present disclosure discloses a thin film transistor, a method for manufacturing thereof, an array substrate and a display device. The method for manufacturing the thin film transistor includes: forming a nanowire active layer on one side of a base substrate; forming a conductive protective layer on one side of the nanowire active layer away from the base substrate; forming an insulating layer on one side of the protective layer away from the nanowire active layer; etching the insulating layer using a dry etching process to form a first via hole exposing a first region of the protective layer and a second via hole exposing a second region of the protective layer; and forming a source-drain layer on one side of the insulating layer away from the protective layer, wherein the source-drain layer includes a first electrode and a second electrode.

A pixel driving circuit and a display panel are provided. The pixel driving circuit includes a source of a second thin film transistor electrically connected to a drain of a first thin film transistor, a gate of a sixth thin film transistor configured to receive a third control signal, a source of the sixth thin film transistor electrically connected to a second node, and a drain of the sixth thin film transistor electrically connected to an anode of a light emitting device.

An electronic device can include a panel; a driver circuit configured to drive the panel; and a transistor disposed in the panel, the transistor including a first electrode disposed on a substrate, an insulation pattern disposed on the substrate, the insulation pattern overlapping with an edge of the first electrode, a second electrode disposed on an upper surface of the insulation pattern, an active layer disposed on the first electrode, the insulation pattern and the second electrode, a gate insulating film disposed on the active layer, and a gate electrode disposed on the gate insulating film, in which a first portion of the active layer overlaps with the first electrode, a second portion of the active layer overlaps with the second electrode, and a channel area of the active layer is between the first portion of the active layer and the second portion of the active layer, and the channel area includes a first channel portion disposed along a side surface of the insulation pattern, and a second channel portion disposed on a portion of the upper surface of the insulation pattern, the second channel portion extending from an edge of the second electrode to the first channel portion.

In a thin film transistor, an increase in off current or negative shift of the threshold voltage is prevented. In the thin film transistor, a buffer layer is provided between an oxide semiconductor layer and each of a source electrode layer and a drain electrode layer. The buffer layer includes a metal oxide layer which is an insulator or a semiconductor over a middle portion of the oxide semiconductor layer. The metal oxide layer functions as a protective layer for suppressing incorporation of impurities into the oxide semiconductor layer. Therefore, in the thin film transistor, an increase in off current or negative shift of the threshold voltage can be prevented.

An anti-stress liquid crystal display structure and a manufacturing method are provided. The anti-stress liquid crystal display structure includes a first substrate, a plurality of thin film transistors, a second substrate, a plurality of pillar-shaped supporting elements, and a liquid crystal layer. The plurality of thin film transistors have a protection layer and include at least one first protruding part and at least one first concave part. One end of each of the pillar-shaped supporting elements is connected to the second substrate, and other end of each of the pillar-shaped supporting elements includes at least one second protruding part and at least one second concave part and is disposed on the protection layer of each of the thin film transistors. The liquid crystal layer is disposed between the first substrate and the second substrate.