Provided is a semiconductor package having a package housing in an engraved surface form and a method of manufacturing the same, wherein the semiconductor package includes: at least one substrate on which at least one semiconductor chip is installed; at least one terminal lead electrically connected to the substrates; electrical connectors for connecting the semiconductor chips to the substrates or the terminal leads; a package housing covering the semiconductor chips, the electrical connectors, and the at least one substrate; at least one stopper which is formed of a material same as that of the package housing, is higher by a certain height than exposed surfaces of the substrates, is disposed on the exposed surfaces of the substrates, or covers at least a part of the exposed surfaces; and at least one heat sink transmitting heat from the semiconductor chips and radiating heat, wherein the at least a part of the exposed surfaces of the at least one substrate is formed on the upper surface, the lower surface, or the upper and lower surfaces of the package housing and the exposed surfaces of the at least one substrate are joined to the heat sinks by using heat transfer connectors interposed therebetween. Accordingly, the full thickness of the heat transfer connectors may be uniformly maintained.

A method includes attaching a first anisotropic conductive film including first conductive particles to a front surface of a substrate structure; compressing a first redistribution structure on the front surface of the substrate structure such that a first redistribution conductor of the first redistribution structure that is exposed is electrically connected by the first conductive particles to a connection terminal or a vertical connection conductor that is exposed from the substrate structure, attaching a second anisotropic conductive film including second conductive particles to a rear surface of the substrate structure; and compressing a second redistribution structure on the rear surface of the substrate structure such that a second redistribution conductor of the second redistribution structure that is exposed is electrically connected by the second conductive particles to the vertical connection conductor.

In some examples, a direct current (DC)-DC power converter package comprises a controller, a conductive member, and a first field effect transistor (FET) coupled to the controller and having a first source and a first drain, the first FET coupled to a first portion of the conductive member. The package also comprises a second FET coupled to the controller and having a second source and a second drain, the second FET coupled to a second portion of the conductive member, the first and second portions of the conductive member being non-overlapping in a horizontal plane. The first and second FETs are non-overlapping.

A display module includes a first substrate; a plurality of micro-pixel packages provided on an upper surface of the first substrate and including a plurality of pixels arranged in two dimensions; a plurality of micro-pixel controllers provided on the upper surface of the first substrate and configured to control the plurality of micro-pixel packages; and a driver integrated chip (IC) configured to transmit a driving signal to the plurality of micro-pixel controllers, wherein upper ends of the plurality of micro-pixel packages are positioned higher than upper ends of the plurality of micro-pixel controllers with respect to the upper surface of the first substrate.

This disclosure relates to a discrete cascode semiconductor device and associated method of manufacture, the device includes: a high voltage depletion mode device die having gate, source and drain terminals arranged on a first major surface thereof; a low voltage enhancement mode device die having a gate and a source terminal formed on a first major surface thereof, and a drain terminal formed on a second major surface opposite the first major surface. The drain terminal of the high voltage device die is mounted on a drain connection; the source terminal of the low voltage device die and the gate terminal of the high voltage device are mounted on a common source connection; and the drain terminal of the low voltage device die is mounted on the source terminal of the high voltage device.

A bonding structure formed on a substrate includes an indium layer and a passivating nickel plating formed on the indium layer. The nickel plating serves to prevent a reaction involving the indium layer.

The present invention provides a display device comprising: a substrate; a wiring electrode disposed on the substrate; a plurality of semiconductor light emitting elements each provided with a conductive electrode electrically connected to the wiring electrode; and an anisotropic conductive layer which is disposed between the conductive electrodes and the wiring electrode and formed of a mixture of conductive particles and an insulating material, wherein the conductive electrodes are provided with a protrusion part protruding toward the wiring electrode.

A composite substrate includes, in this order: a ceramic plate; a metal layer containing at least one selected from the group consisting of aluminum and an aluminum alloy; and a thermal sprayed layer containing at least one selected from the group consisting of copper and a copper alloy, and an intermetallic compound containing copper and aluminum as constituent elements is scattered between the metal layer and the thermal sprayed layer.

A semiconductor device includes: an insulated circuit substrate including first and second conductive layers on a top surface side; a first semiconductor chip mounted on the first conductive layer; a second semiconductor chip mounted on the second conductive layer; a printed circuit board including a first lower-side wiring layer arranged to be opposed to the first semiconductor chip, and a second lower-side wiring layer arranged to be opposed to the second semiconductor chip, the printed circuit board being provided with a curved part curved toward the insulated circuit substrate; a first connection member arranged to connect the first semiconductor chip with the first lower-side wiring layer; a second connection member arranged to connect the second semiconductor chip with the second lower-side wiring layer; and a third connection member arranged to connect the first conductive layer with the second lower-side wiring layer at the curved part.

A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.