A semiconductor package includes: a lead frame having a plurality of blocks of uniform size and laterally spaced apart from one another with uniform spacing; a first semiconductor die attached to a first group of the blocks; electrical conductors connecting a plurality of input/output (I/O) terminals of the first semiconductor die to a second group of the blocks, at least some blocks of the second group being laterally spaced outward from the blocks of the first group; and a mold compound encapsulating the first semiconductor die and the electrical conductors. Corresponding methods of producing the semiconductor package are also described.

A solder alloy, includes: about 3 wt % to about 15 wt % of Sb; about 0.01 wt % to about 1.5 wt % of Te; and about 0.005 wt % to about 1 wt % of at least one element selected from the group consisting of Zn, Co, and Cr; and a balance of Sn.

A method for producing an optoelectronic component and an optoelectronic component are disclosed. In an embodiment a method includes providing a carrier having a pedestal with a support surface, applying a liquid joining material with filler particles to the support surface of the pedestal and applying a radiation emitting semiconductor chip with a mounting surface, which is larger than the support surface of the pedestal to the liquid joining material such that the joining material forms a joining layer between the support surface of the pedestal and the mounting surface of the semiconductor chip and the joining material at least partially fills only a recess, which is limited by a part of the mounting surface projecting beyond the support surface.

The one end portion of the connector of the semiconductor device includes: a horizontal portion; a first inclined portion that is connected to the horizontal portion and is located closer to the tip end side of the one end than the horizontal portion, and the first inclined portion having a shape inclined downward from the horizontal portion; and a control bending portion that is connected to the first inclined portion and positioned at the tip of the one end portion, and the control bending portion bent downwardly along the bending axis direction. The lower surface of the control bending portion is in contact with an upper surface of the second terminal.

A SiC power semiconductor device includes: a power semiconductor die including SiC and a metallization layer, wherein the metallization layer includes a first metal; a die carrier, wherein the power semiconductor die is arranged over the die carrier such that the metallization layer faces the die carrier, the die carrier being at least partially covered by a plating that includes Ni; and a first intermetallic compound arranged between the power semiconductor die and the plating and including Ni.sub.3Sn.sub.4.

An integrated circuit assembly may be formed comprising at least one integrated circuit device, a heat dissipation device having a thermal contact surface with at least one containment structure extending into or from the heat dissipation device at the thermal contact surface, and a thermal interface material between the at least one integrated circuit device and the heat dissipation device, wherein the thermal interface material contacts the at least one containment structure of the heat dissipation device.

In a method for connecting components during production of power electronics modules or assemblies, surfaces of the components have a metallic surface layer upon supply, or are furnished therewith, wherein the layer has a surface that is smooth enough to allow direct bonding or is smoothed to obtain a surface that is smooth enough to allow direct bonding. The surface layers of the surfaces that are to be connected are then pressed against each other with a pressure of at least 5 MPa at elevated temperature, so that they are joined to each other, forming a single layer. The method enables simple, rapid connection of even relatively large contact surfaces, which satisfies the high requirements of power electronics modules.

An electronic module has a first substrate 11, an electronic element 13 provided on one side of the first substrate 13, a second substrate 21 provided on one side of the electronic element 13 and a positioning part 200 extending from the first substrate 11 to one side and abutting a circumferential part of the second substrate 21, or extending from the second substrate 21 to the other side and abutting against a circumferential part of the first substrate 11.

Embodiments of the disclosure relate to an MIO substrate with integrated jet cooling for electronic modules and a method of forming the same. In one embodiment, a substrate for an electronic module includes a thermal compensation base layer having an MIO structure and a cap layer overgrown on the MIO structure. A plurality of orifices extends through the thermal compensation base layer between an inlet face and an outlet face positioned opposite to the inlet face, defining a plurality of jet paths. A plurality of integrated posts extends outward from the cap layer, wherein each integrated post of the plurality of integrated posts is positioned on the outlet face between each orifice of the plurality of orifices.

Disclosed herein are structures and assemblies that may be used for thermal management in integrated circuit (IC) packages.