Provided are an ultrasonic fingerprint identification circuit, a driving method thereof, and a display device. The ultrasonic fingerprint identification circuit comprises fingerprint identification units each including an ultrasonic fingerprint identification sensor connected to a first node; a control module connected to a composite signal line, a first control signal line and the first node and configured to provide a reset potential to the first node and to provide a pull-up potential to the first node in response to a first level provided by the composite signal line; a reading module connected to a second control signal line, the first node and a reading signal line, and configured to read a detection signal of the first node. The first control signal line connected to one fingerprint identification unit is reused as the second control signal line connected to another fingerprint identification unit.

Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. The semiconductor active layer and the sacrificial layer may be selectively etched in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. The capping layer and the first portion of the semiconductor active layer may be selectively etched to thereby expose the sacrificial layer. The sacrificial layer may be selectively removed from between the first portion of the semiconductor active layer and the handling substrate to thereby define a suspended integrated circuit chip encapsulated by the capping layer.

A display device may include a light emitting element, a buffer layer, a gate insulation layer, and a switching element. A refractive index of the gate insulation layer may be equal to a refractive index of the buffer layer. The switching element may be electrically connected to the light emitting element and may include an active layer and a gate electrode. The active layer may be positioned between the buffer layer and the gate insulation layer and may directly contact at least one of the buffer layer and the gate insulation layer. The gate insulation layer may be positioned between the active layer and the gate electrode and may directly contact at least one of the active layer and the gate electrode.

A display device includes an array substrate, a second substrate and a black matrix. The array substrate includes a first substrate, at least one electrostatic protecting component and a shielding layer. The first substrate has a display region and a peripheral region located outside the display region. The electrostatic protecting component is disposed on the first substrate in the peripheral region, and the electrostatic protecting component includes a semiconductor layer. The shielding layer includes an insulating material, and the shielding layer is disposed on the first substrate in the peripheral region, wherein the shielding layer overlaps the semiconductor layer. The second substrate is opposite to the first substrate. The black matrix is disposed between the second substrate and the first substrate. The shielding layer is disposed between the black matrix and the first substrate.

Ferroelectric field effect transistors (FeFETs) having band-engineered interface layers are described. In an example, an integrated circuit structure includes a semiconductor channel layer above a substrate. A metal oxide material is on the semiconductor channel layer, the metal oxide material having no net dipole. A ferroelectric oxide material is on the metal oxide material. A gate electrode is on the ferroelectric oxide material, the gate electrode having a first side and a second side opposite the first side. A first source/drain region is at the first side of the gate electrode, and a second source/drain region is at the second side of the gate electrode.

A display device includes: a pixel section provided between a pair of substrates and including plural pixels; one or plural active components disposed in a frame region around the pixel section on one substrate of the pair of substrates; an insulating film provided in the frame region on the one substrate to cover the one or plural active components; and a sealing layer provided to seal the pixel section and cover an end edge portion of the insulating film in the frame region.

A display apparatus includes a first substrate, a first dummy substrate on the first substrate, and a second dummy substrate extending from the first dummy substrate and bent. The second dummy substrate is on different side surfaces of the first substrate in a first direction. The display apparatus also includes a plurality of pixels on the first dummy substrate, a gate driver on the second dummy substrate and connected to the pixels, and a data driver connected to one side of the first dummy substrate in a second direction crossing the first direction and connected to the pixels.

A thin film transistor is provided, and includes a gate electrode, a first gate dielectric layer, a second gate dielectric layer, a channel layer, a source electrode and a drain electrode. The gate electrode is disposed on a substrate. The first gate dielectric layer is disposed on the gate electrode and the substrate, and has a radio of the number of silicon-hydrogen bonds to the number of nitrogen-hydrogen bonds, in which the ratio is between 0.2 and 1.0. The second gate dielectric layer is disposed on the first gate dielectric layer, and has a radio of the number of silicon-hydrogen bond to the number of nitrogen-hydrogen bonds, in which the ratio is between 0.01 and 0.2. The channel layer is disposed on the second gate dielectric layer. The source electrode and drain electrode are disposed on the channel layer and located at two opposite sides of the channel layer.

The present invention provides an array substrate and a manufacture method thereof. The array substrate, by locating both a black matrix and a color resist layer on the array substrate, and locating the color resist layer on the TFT layer prevents the bad influence to the color resist layer from the high temperature TFT process, and accordingly to make the liquid crystal panel with higher display quality. The manufacture method of the array substrate, first forms a black matrix on the substrate, and second implements TFT manufacture process on the black matrix, and then forms a color resist layer after the TFT manufacture. Accordingly, both the black matrix and the color resist layer manufactured on the array substrate can be achieved, and with forming the color resist layer after the TFT manufacture to prevent the bad phenomenon due to bubbles generated by the color resist volatilization from the high temperature TFT process, and accordingly to effectively make the liquid crystal panel with higher display quality and raise production yield.

A display device includes: a substrate; a first thin film transistor unit disposed on the substrate and comprising a first active layer comprising a silicon layer, wherein the first active layer comprises a channel region, a source region and a drain region; a second thin film transistor unit disposed on the substrate and comprising a second active layer comprising a metal oxide layer; and a display medium disposed on the first thin film transistor unit and the second thin film transistor unit. Herein, a thickness of the silicon layer in the channel region is less than or equal to a thickness of the silicon layer in the source region.