The present disclosure provides a method for making a thin film transistor (TFT), a TFT, a back plate and a display device. The TFT includes: a gate electrode, a source, a drain, a dielectric layer and an active layer on the dielectric layer. The active layer includes at least one a-Si area and at least one p-Si area. This can reduce leakage current and reduce the technical complexity of the large-channel TFT.

The present application discloses a thin film transistor. The thin film transistor includes a base substrate; an active layer; an etch stop layer on a side of the active layer distal to the base substrate; and a source electrode and a drain electrode on a side of the etch stop layer distal to the active layer. The active layer includes a channel region, a source electrode contact region, and a drain electrode contact region. An orthographic projection of the etch stop layer on the base substrate surrounds an orthographic projection of the drain electrode contact region on the base substrate. An orthographic projection of the source electrode contact region on the base substrate at least partially peripherally surrounding the orthographic projection of the etch stop layer on the base substrate.

Certain aspects of the present disclosure provide a variable transistor-based capacitive element implemented on a glass or dielectric substrate. Such a variable transistor-based capacitive element may be suitable for use as a tunable capacitor in a passive-on-glass (POG) device, for example. One example device having a tunable capacitance generally includes a glass or dielectric substrate and a transistor disposed above the glass or dielectric substrate. The transistor has a gate region, a drain region, and a source region, wherein a capacitance of the transistor is configured to vary based on a voltage between the gate region and the drain region.

A display device including a substrate having thin film transistors (TFT) comprising: the TFT including an oxide semiconductor film, a gate electrode and an insulating film formed between the oxide semiconductor film and the gate electrode, wherein a first aluminum oxide film and a second aluminum oxide film, which is formed on the first aluminum oxide film, are formed between the insulating film and the gate electrode, an oxygen concentration in the first aluminum oxide film is bigger than an oxygen concentration in the second aluminum oxide film.

A thin film transistor, a manufacturing method thereof, an array substrate and a display device are disclosed. The thin film transistor includes an active layer, as well as a source and a drain above the active layer, wherein the active layer includes a carrier trapping portion configured to trap photo-generated majority carriers.

A display device including a pixel section provided between a pair of substrates and including plural pixels; one or plural active components disposed in a frame region around the pixel section on one substrate of the pair of substrates; an insulating film provided in the frame region on the one substrate to cover the one or plural active components; and a sealing layer provided to seal the pixel section and cover an end edge portion of the insulating film in the frame region.

A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.

A display device includes a substrate, a plurality of pixels above the substrate, each of the pixels including a light emitting element, a display region including the plurality of pixels, a thin film transistor which each of the plurality of pixels includes, a protective film including a first inorganic insulating material and located between the thin film transistor and the light emitting element, a sealing film including a second inorganic insulating material and covering the light emitting element, and at least one through hole located in the display region and passing through the substrate, the protective film, and the sealing film, wherein the second inorganic insulating material is in direct contact with the protective film in a first region located between the through hole and the pixels.

A method of manufacturing a transistor comprising providing a substrate, a region of semiconductive material on the substrate, and a region of electrically conductive material on the region of semiconductive material; forming a covering of resist material over said regions; forming a depression in a surface of the covering of resist material that extends over a first portion of said region of conductive material, said first portion separating second and third portions of the conductive region; removing resist material located under said depression to form a window through said covering, exposing said first portion; removing said first portion to expose a connecting portion of the region of semiconductive material that connects the second and third portions; forming a layer of dielectric material over the exposed connecting portion; and forming a layer of electrically conductive material over said layer of dielectric material.

A display panel measures a contact resistance of an adhesive portion to evaluate adhesion quality of an integrated circuit mounted thereon. The display panel includes a plurality of light-emitting elements, a first pad part including a plurality of first effective pads electrically connected to the light-emitting elements, and n (n being a natural number equal to or greater than 2) first measuring pads insulated from the light-emitting elements, a conductive adhesive film on the first pad part and including a plurality of conductive balls, an integrated circuit on the conductive adhesive film, and including an internal line electrically connected to the first measuring pads by the conductive balls, and a second pad part including a plurality of second effective pads electrically connected to the first effective pads, and 2n second measuring pads electrically connected to the first measuring pads.